Why RISC-V doesn't (yet) support KVM

Posted May 21, 2021 1:45 UTC (Fri) by ncm (guest, #165)
Parent article: Why RISC-V doesn't (yet) support KVM

If it's not frozen, then by definition it might still change. Are kernel maintainers prepared to support more than one version of RISC-V virtualization?

To me the worst continuing omission is the B extension, and the worst missing bit of that is the POPCOUNT instruction, which really should be in with the base instructions alongside ADD and AND. I gather some lunatics are agitating to make it optional even in B, which is insane. POPCOUNT has been in or lately added to every production architecture ever, for reasons. (And, no, trap emulation would be much worse than useless.)

Why RISC-V doesn't (yet) support KVM

Posted May 21, 2021 7:43 UTC (Fri) by pbonzini (subscriber, #60935) [Link]

Indeed, just give me CLZ/CTZ/POPCOUNT/ROL/ROR/SEXT in the base instruction set and call it a day...

Why RISC-V doesn't (yet) support KVM

Posted May 21, 2021 10:54 UTC (Fri) by khim (subscriber, #9252) [Link] (3 responses)

> Are kernel maintainers prepared to support more than one version of RISC-V virtualization?

Why would that be a problem? AMD and Intel use totally different schemes and they both are supported.

And I think being implemented in ASIC which is shipping should be considered “effectively frozen”. I can see how people may implement thousands of different things on FPGA. Supporting these would be a nightmare from practical POV. And FPGA implementation can definitely be changed thus it's not “effectively frozen” anyway. But if something is already in ASIC it couldn't ever be changed (on that specific ASIC) thus I think kernel should support it.

Kernel supports lots of devices (WiFi and others) which only support draft of some spec or another… why RISC-V extensions should be different?

Why RISC-V doesn't (yet) support KVM

Posted May 21, 2021 15:11 UTC (Fri) by mss (subscriber, #138799) [Link] (2 responses)

> Why would that be a problem? AMD and Intel use totally different schemes and they both are supported.

It's a waste of effort to implement what's effectively the same thing two different ways.
And these aren't trivial things.

Why RISC-V doesn't (yet) support KVM

Posted May 23, 2021 7:38 UTC (Sun) by ssmith32 (subscriber, #72404) [Link] (1 responses)

It's not a waste of effort for the people who are stuck with one implementation or the other: in short, the users of linux. Particularly when that implementation is baked into asic hardware.

Why RISC-V doesn't (yet) support KVM

Posted May 23, 2021 11:57 UTC (Sun) by mss (subscriber, #138799) [Link]

My comment was more about not having two different hardware schemes in the first place (like VMX and SVM for x86).