| From: |
| Bibo Mao <maobibo-AT-loongson.cn> |
| To: |
| Huacai Chen <chenhuacai-AT-kernel.org>, Jianmin Lv <lvjianmin-AT-loongson.cn> |
| Subject: |
| [RFC v2 0/2] irqchip/loongson-eiointc: Add multiple interrupt pin routing support |
| Date: |
| Wed, 28 Aug 2024 15:06:01 +0800 |
| Message-ID: |
| <20240828070603.3518753-1-maobibo@loongson.cn> |
| Cc: |
| WANG Xuerui <kernel-AT-xen0n.name>, Thomas Gleixner <tglx-AT-linutronix.de>, loongarch-AT-lists.linux.dev, linux-kernel-AT-vger.kernel.org, linux-mips-AT-vger.kernel.org |
| Archive-link: |
| Article |
There are four times about EIOINTC_REG_ISR register group access in
eiointc irq handler, in order to get all irq status about 256 interrupt
vectors. It causes four times VM-exits since eiointc register are
software emulated, here multiple interrupt pin routing is introduced
and each 64 interrupt vector is routed to one interrupt pin.
With this method, there will be only on one EIOINTC_REG_ISR register
group acces in irq handler, it will reduce VM-exits.
---
v1 ... v2:
1. Add different route_info handler as eiointc interrupt handler
parameter, so that irq handler can read corresponding ISR
2. Call function set_csr_ecfg() to enable cpu interrupt pin in eiointc
driver inside.
---
Bibo Mao (2):
irqchip/loongson-eiointc: Route interrupt parsed from acpi table
irqchip/loongson-eiointc: Add multiple interrupt pin routing support
drivers/irqchip/irq-loongson-eiointc.c | 83 +++++++++++++++++++++++---
1 file changed, 75 insertions(+), 8 deletions(-)
base-commit: 3ec3f5fc4a91e389ea56b111a73d97ffc94f19c6
--
2.39.3
