An atomic instruction is a full barrier to everything?

Posted Jun 5, 2024 11:14 UTC (Wed) by farnz (subscriber, #17727)
In reply to: An atomic instruction is a full barrier to everything? by epa
Parent article: An instruction-level BPF memory model

Yes, and that's implicit in virtually all descriptions of memory ordering; what we normally talk about is "happens-before" ordering, where we say that A happens-before B if and only if we can deduce that A must have happened given that we can demonstrate that B has happened.

There's also sometimes the need to talk about whether a happens-before ordering is global (i.e. if thread X sees that A happens-before B, then thread Y must agree that A happens-before B) or local (if thread X sees that A happens-before B, thread Y could still see that B happens-before A, that A happens-before B, or that there's no ordering relationship between A and B). This is, I think what you were reaching towards; an atomic instruction does not always guarantee a global ordering, but on x86, it's defined as doing so (LOCK prefixes are defined this way).