| From: |
| Swapnil Jakhade <sjakhade-AT-cadence.com> |
| To: |
| <vkoul-AT-kernel.org>, <kishon-AT-kernel.org>, <robh+dt-AT-kernel.org>, <krzysztof.kozlowski+dt-AT-linaro.org>, <conor+dt-AT-kernel.org>, <linux-phy-AT-lists.infradead.org>, <linux-kernel-AT-vger.kernel.org>, <devicetree-AT-vger.kernel.org> |
| Subject: |
| [PATCH v3 0/5] PHY: Add support for dual refclk configurations in Cadence Torrent PHY driver |
| Date: |
| Thu, 21 Dec 2023 17:20:46 +0100 |
| Message-ID: |
| <20231221162051.2131202-1-sjakhade@cadence.com> |
| Cc: |
| <mparab-AT-cadence.com>, <sjakhade-AT-cadence.com>, <rogerq-AT-kernel.org>, <s-vadapalli-AT-ti.com> |
| Archive-link: |
| Article |
This patch series extends Torrent PHY driver functionality to support
dual input reference clocks.
It also adds support for following multilink configurations:
- PCIe(100MHz) + USXGMII(156.25MHz)
- USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)
The changes have been validated on TI J721E and J7200 platforms.
v1 of the patch series can be found at [1].
Version History:
v3:
- Updated clock description in DT documentation
- Added Acked-by from Conor
v2:
- Rename refclk1 to pll1_refclk in bindings and in driver
- Simplify clock-names as suggested by Rob
[1] https://lore.kernel.org/linux-phy/20230724150002.5645-1-s...
Swapnil Jakhade (5):
dt-bindings: phy: cadence-torrent: Add optional input reference clock
for PLL1
phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink
configuration
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)
multilink configuration
dt-bindings: phy: cadence-torrent: Add a separate compatible for TI
J7200
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)
multilink config for TI J7200
.../bindings/phy/phy-cadence-torrent.yaml | 11 +-
drivers/phy/cadence/phy-cadence-torrent.c | 705 +++++++++++++++++-
2 files changed, 710 insertions(+), 6 deletions(-)
--
2.25.1
