Intel's "redundant prefix issue"

Posted Nov 17, 2023 23:14 UTC (Fri) by Wol (subscriber, #4433)
In reply to: Intel's "redundant prefix issue" by IanKelling
Parent article: Intel's "redundant prefix issue"

>>> Other architectures like ARM implement micro-code as circuitry (not in software).

>>One might question whether architectures like ARM even have microcode.

>Right, it is probably more accurate to say they don't have microcode. I should have said that.

In which case, doesn't that make it un-updateable full stop?

If it's implemented as circuitry, you can't change it (except by things like blowing PROM fuses ...)

If you want to make it do something else, you have to load a program of some sort (and the fact that microcode typically is loaded every time on boot is overwhelming evidence that microcode is software).

Okay, this might not be the best analogy (or it might be spot on), but isn't microcode just programming an FPGA in the CPU? Not all of the CPU will be programmable like that, but that's pretty much what's going on, no?

(Oh, and I'll just throw in the fact that some - probably most - mini-computer CPUs from the 80s and maybe earlier had microcode - the Pr1me 50-series certainly did. If you ran INFORMATION (the Pr1me version of Pick) you got a microcode update to your CPU to optimise it for running the database.)

Cheers,
Wol

Intel's "redundant prefix issue"

Posted Nov 18, 2023 1:01 UTC (Sat) by excors (subscriber, #95769) [Link]

> Okay, this might not be the best analogy (or it might be spot on), but isn't microcode just programming an FPGA in the CPU?

I don't think so. The reverse-engineering of Intel Goldmont at https://misc0110.net/files/cpu_woot23.pdf says the microcode is stored in MSROM (microcode sequencer ROM), with space for about 8K 'triads' (each consisting of 3 uops and a sequence word), plus a much smaller MSRAM for microcode patches (which are loaded at boot time by the BIOS/OS), and some registers to configure where the patches are applied.

When the CPU's instruction decoder finds a complex instruction, the microcode sequencer uses the opcode to determine the entry point into the MSROM, then it reads a triad from MSROM (or MSRAM if that address has been patched) and issues the uops for execution, then uses the sequence word to determine the next triad, until it has finished that instruction.

It sounds debatable whether it should count as software or as a fancy LUT, but in any case it's nothing like an FPGA, it's just data in memory that gets processed by fixed hardware.