Intel's "redundant prefix issue"
Intel's "redundant prefix issue"
Posted Nov 16, 2023 22:49 UTC (Thu) by willy (subscriber, #9762)In reply to: Intel's "redundant prefix issue" by cesarb
Parent article: Intel's "redundant prefix issue"
That's not quite an accurate description of how Intel currently decodes instructions. See https://en.wikichip.org/wiki/intel/microarchitectures/sky...(client)#Front-end for a recent implementation.
In brief, there is one complex decoder which can emit up to four uops, three simple decoders which can emit up to one uop each _and_ a microcode sequencer which can emit up to four uops per cycle (but while it's running, the decoders are disabled).
I presume that "new microcode" will intercept insns that otherwise would have been natively executed, and issue different uops from the ones that would have been issued by hardware.