Intel's "redundant prefix issue"

How do you know that? AArch32 and AArch64 are radically different ISAs and modern ARM CPUs support both. This strongly suggests that there are some internal core with two switchable translation components. We know that NEC V20 did that with two switchable microcode blocks.

Without us seeing that block is organized in ARM CPUs we wouldn't know whether what it uses may be classified as microcode or not.

As lest more complex chips (like Apple's M1/M2/M3) are likely to include microcode which is used for at least some instructions.

Modern AMD and Intel CPUs don't use microcode for all instructions, too, only more complicated ones are microcoded.