Intel's "redundant prefix issue"

Posted Nov 16, 2023 6:26 UTC (Thu) by zaitseff (subscriber, #851)
In reply to: Intel's "redundant prefix issue" by donald.buczek
Parent article: Intel's "redundant prefix issue"

> If you were to design a ISA from scratch [...]

Definitely off topic, but I personally find the RISC-V architecture [1] to be very nicely and cleanly defined, for 32-bit, 64-bit and even 128-bit. Much cleaner than ARM, IMHO!

[1] https://riscv.org/technical/specifications/

Intel's "redundant prefix issue"

Posted Nov 16, 2023 7:38 UTC (Thu) by ballombe (subscriber, #9523) [Link] (2 responses)

risc-V is a copycat of the old '90 DEC alpha ISA without any modern improvement.
It is not even fully 64bit for multiplication and division.

aarch64 is much nicer.

Intel's "redundant prefix issue"

Posted Nov 16, 2023 12:03 UTC (Thu) by anton (subscriber, #25547) [Link] (1 responses)

It is not even fully 64bit for multiplication and division.

What do you mean by that? In RV64G mul performs a 64-bit*64-bit multiplication, div performs a signed 64-bit/64-bit division, and divu performs an unsigned 64-bit/64-bit division. Alpha does not have an integer division instruction.

Intel's "redundant prefix issue"

Posted Nov 16, 2023 18:04 UTC (Thu) by ballombe (subscriber, #9523) [Link]

Risc-V 64 does not have full 128bit / 64bit -> 64bit division, instead it has only 64bit/64bit->64bit division
(like aarch64)

Compared to aarch64, it lacks addition with carry, subtraction with carry and
"addmul" (that is (a,b,c) -> a*b+c where a,b,c are 64bit and the result is 128bit)