Large folios for anonymous memory

Posted Jul 8, 2023 8:13 UTC (Sat) by yuzhao@google.com (guest, #132005)
In reply to: Large folios for anonymous memory by james
Parent article: Large folios for anonymous memory

Zen and later AMD CPUs support *transparent* TLB coalescing. They call it PTE coalescing (8*4KB).

The contiguous block entries (16*4KB) on (older) Armv8-A CPUs require OS to set the contiguous bit in PTEs, hence not transparent. The (newer) ARMv8.2-A supports Hardware Page Aggregation (HPA), which like the AMD PTE coalescing is also transparent but at a smaller granularity (4*4KB).

Intel at the moment doesn't provide either.

Large folios for anonymous memory

Posted Jul 13, 2023 7:37 UTC (Thu) by ikitayama (subscriber, #51589) [Link] (1 responses)

Even for 64KB granule systems as well?
Then 4*64KB.

Large folios for anonymous memory

Posted Jul 13, 2023 20:21 UTC (Thu) by yuzhao@google.com (guest, #132005) [Link]

For the 64KB (ARM) page size, contiguous block entries need to be 32*64KB=2MB aligned.