| From: |
| Cai Huoqing <cai.huoqing-AT-linux.dev> |
| To: |
| fancer.lancer-AT-gmail.com |
| Subject: |
| [PATCH v4 0/4] dmaengine: dw-edma: Add support for native HDMA |
| Date: |
| Tue, 21 Feb 2023 11:46:51 +0800 |
| Message-ID: |
| <20230221034656.14476-1-cai.huoqing@linux.dev> |
| Cc: |
| Cai Huoqing <cai.huoqing-AT-linux.dev>, Gustavo Pimentel <gustavo.pimentel-AT-synopsys.com>, Vinod Koul <vkoul-AT-kernel.org>, Jingoo Han <jingoohan1-AT-gmail.com>, Lorenzo Pieralisi <lpieralisi-AT-kernel.org>, Krzysztof Wilczyński <kw-AT-linux.com>, Rob Herring <robh-AT-kernel.org>, Bjorn Helgaas <bhelgaas-AT-google.com>, linux-kernel-AT-vger.kernel.org, dmaengine-AT-vger.kernel.org, linux-pci-AT-vger.kernel.org |
| Archive-link: |
| Article |
Add support for HDMA NATIVE, as long the IP design has set
the compatible register map parameter-HDMA_NATIVE,
which allows compatibility for native HDMA register configuration.
The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP.
And the native HDMA registers are different from eDMA,
so this patch add support for HDMA NATIVE mode.
HDMA write and read channels operate independently to maximize
the performance of the HDMA read and write data transfer over
the link When you configure the HDMA with multiple read channels,
then it uses a round robin (RR) arbitration scheme to select
the next read channel to be serviced.The same applies when
youhave multiple write channels.
The native HDMA driver also supports a maximum of 16 independent
channels (8 write + 8 read), which can run simultaneously.
Both SAR (Source Address Register) and DAR (Destination Address Register)
are aligned to byte.
Cai huoqing (4):
dmaengine: dw-edma: Rename dw_edma_core_ops structure to
dw_edma_plat_ops
dmaengine: dw-edma: Create a new dw_edma_core_ops structure to
abstract controller operation
dmaengine: dw-edma: Add support for native HDMA
dmaengine: dw-edma: Add HDMA DebugFS support
v3->v4:
[1/4]
1.Update the structure name dw_edma_plat_ops in commit log
2.Fix code stytle.
[2/4]
3.Refactor dw_edma_interrupt() and related callbacks to
make the code more readable, the calls hierarchy like this:
irq: dw_edma_interrupt_{write,read}()
+-> dw_edma_core_handle_int() (dw-edma-v0-core.c)
+-> dw_edma_v0_core_status_done_int() (dw-edma-v0-core.c)
+-> dw_edma_v0_core_clear_done_int() (dw-edma-v0-core.c)
+-> dw_edma_done_interrupt() (dw-edma-core.c)
+-> dw_edma_v0_core_status_abort_int() (dw-edma-v0-core.c)
+-> dw_edma_v0_core_clear_abort_int() (dw-edma-v0-core.c)
+-> dw_edma_abort_interrupt() (dw-edma-core.c)
4.Use the dw_edma_v0_core name for the dw_edma_core_ops structure instance.
[3/4]
5.Fix weird indentation of control1, func_num, etc.
6.Include 'linux/io-64-nonatomic-lo-hi.h' to fix warning.
7.Refactor dw_edma_core_handle_int related callback in dw_hdma_v0_core ops.
[4/4]
8.Add field watermark_en, func_num, qos, msi_watermark,etc.
9.Make variables reverse xmas tree order.
10.Declare const for 'struct dw_hdma_debugfs_entry'
v3 link:
https://lore.kernel.org/lkml/20230213132411.65524-1-cai.h...
drivers/dma/dw-edma/Makefile | 8 +-
drivers/dma/dw-edma/dw-edma-core.c | 77 ++---
drivers/dma/dw-edma/dw-edma-core.h | 56 ++++
drivers/dma/dw-edma/dw-edma-pcie.c | 4 +-
drivers/dma/dw-edma/dw-edma-v0-core.c | 73 ++++-
drivers/dma/dw-edma/dw-edma-v0-core.h | 14 +-
drivers/dma/dw-edma/dw-hdma-v0-core.c | 302 +++++++++++++++++++
drivers/dma/dw-edma/dw-hdma-v0-core.h | 17 ++
drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 181 +++++++++++
drivers/dma/dw-edma/dw-hdma-v0-debugfs.h | 22 ++
drivers/dma/dw-edma/dw-hdma-v0-regs.h | 129 ++++++++
drivers/pci/controller/dwc/pcie-designware.c | 2 +-
include/linux/dma/edma.h | 7 +-
13 files changed, 807 insertions(+), 85 deletions(-)
create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.c
create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.h
create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.c
create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.h
create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-regs.h
--
2.34.1
