CXL 1: Management and tiering

Posted May 15, 2022 3:17 UTC (Sun) by marcH (subscriber, #57642)
In reply to: CXL 1: Management and tiering by MattBBaker
Parent article: CXL 1: Management and tiering

> instead of getting surprised when memory access is magically slow.

Well, it's not like single-thread performance is deterministic either. However I agree shared memory is really crossing a line, it's the biggest programming footgun ever invented by hardware engineers.

Message passing requires an extra programming effort but unlike shared memory, performance and correctness issues can be traced and debugged in a reasonable amount of time.

https://queue.acm.org/detail.cfm?id=3212479

> Caches are large, but their size isn't the only reason for their complexity. The cache coherency protocol is one of the hardest parts of a modern CPU to make both fast and correct. Most of the complexity involved comes from supporting a language in which data is expected to be both shared and mutable as a matter of course.

CXL 1: Management and tiering

Posted May 16, 2022 16:30 UTC (Mon) by ballombe (subscriber, #9523) [Link] (1 responses)

> Message passing requires an extra programming effort but unlike shared memory, performance and correctness issues can be traced and debugged in a reasonable amount of time.

But message passing often requires more total memory for the same task.
And often the performance issue is traced to "not enough memory by node".
So...

CXL 1: Management and tiering

Posted May 17, 2022 8:27 UTC (Tue) by sdalley (subscriber, #18550) [Link]

Personally, I'm more than happy to trade a little more memory for a little more sanity.

And message passing needn't consume more memory if the message buffer simply changes hands between owners rather than being copied. A good interface to such a message interface can also ensure, under the hood, that references to buffers no longer owned are always NULLed.