Pointer tagging for x86 systems

Posted Mar 29, 2022 3:01 UTC (Tue) by mtaht (subscriber, #11087)
In reply to: Pointer tagging for x86 systems by abufrejoval
Parent article: Pointer tagging for x86 systems

Everywhere I turn I see portions of the ideas that were in the mill computer's far more unified versions, gradually being retrofitted into existing architectures.

I wish they'd build it, even just as a virtual machine. It would help people to think better about where we should have started going in the 90s, especially securitywise, when it came to cpu architectures.

Take out some popcorn and watch their talk about security... https://millcomputing.com/docs/#security

Pointer tagging for x86 systems

Posted Mar 29, 2022 5:03 UTC (Tue) by pabs (subscriber, #43278) [Link]

Is there any prospect of Mill resulting in some gateware or hardware that people can use? Or will it remain something that doesn't exist outside the designers minds, talks, documentation and patents?

Pointer tagging for x86 systems

Posted Mar 29, 2022 15:11 UTC (Tue) by willy (subscriber, #9762) [Link]

But the Mill is legit crazy. I forget whether they track dirtiness on a per byte or per bit level, but that level of detail in tracking dirtiness can only hurt. If anything, we should track dirtiness at a super-cache-line level and move things around in a group of two or four cache lines. Of course, that comes with a false sharing problem, which is why it hasn't happened yet.

There's always trade-offs and people can have a real conversation about whether 32, 64 or 128 bytes is the correct size of a cache line, but there's a knee to this curve and 1-4 bytes is outside the scope of sane conversation.