| From: |
| wefu-AT-redhat.com |
| To: |
| anup.patel-AT-wdc.com, atish.patra-AT-wdc.com, palmerdabbelt-AT-google.com, guoren-AT-kernel.org, christoph.muellner-AT-vrull.eu, philipp.tomsich-AT-vrull.eu, hch-AT-lst.de, liush-AT-allwinnertech.com, wefu-AT-redhat.com, lazyparser-AT-gmail.com, drew-AT-beagleboard.org |
| Subject: |
| [PATCH 0/2] riscv: Add RISC-V svpbmt extension supports |
| Date: |
| Wed, 13 Oct 2021 02:33:42 +0800 |
| Message-ID: |
| <20211012183344.105637-1-wefu@redhat.com> |
| Cc: |
| linux-riscv-AT-lists.infradead.org, linux-kernel-AT-vger.kernel.org, taiten.peng-AT-canonical.com, aniket.ponkshe-AT-canonical.com, heinrich.schuchardt-AT-canonical.com, gordan.markus-AT-canonical.com, guoren-AT-linux.alibaba.com, arnd-AT-arndb.de, wens-AT-csie.org, maxime-AT-cerno.tech, dlustig-AT-nvidia.com, gfavor-AT-ventanamicro.com, andrea.mondelli-AT-huawei.com, behrensj-AT-mit.edu, xinhaoqu-AT-huawei.com, huffman-AT-cadence.com, mick-AT-ics.forth.gr, allen.baum-AT-esperantotech.com, jscheid-AT-ventanamicro.com, rtrauben-AT-gmail.com, Fu Wei <fu.wei-AT-linaro.org> |
| Archive-link: |
| Article |
From: Fu Wei <fu.wei@linaro.org>
This patch follows the standard pure RISC-V Svpbmt extension in
privilege spec to solve the non-coherent SOC DMA synchronization
issues.
Wei Fu (2):
dt-bindings: riscv: Add mmu-supports with svpbmt
riscv: Add RISC-V svpbmt supports
.../devicetree/bindings/riscv/cpus.yaml | 5 +++
arch/riscv/include/asm/fixmap.h | 2 +-
arch/riscv/include/asm/pgtable-64.h | 8 ++--
arch/riscv/include/asm/pgtable-bits.h | 41 ++++++++++++++++++-
arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++----
arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++
arch/riscv/mm/init.c | 5 +++
7 files changed, 117 insertions(+), 15 deletions(-)
--
2.25.4
