Top-tier memory management

Posted May 30, 2021 7:11 UTC (Sun) by pabs (subscriber, #43278)
Parent article: Top-tier memory management

I wonder if this sort of thing could allow driving memory sticks of different speeds at different rates and preferring the faster ones.

Top-tier memory management

Posted May 30, 2021 8:06 UTC (Sun) by flussence (guest, #85566) [Link] (2 responses)

That sounds like a nice thing to have, but it seems more likely we'll have practical nuclear fusion before mainboards that support independent memory channel clocks.

Top-tier memory management

Posted May 30, 2021 8:47 UTC (Sun) by Cyberax (✭ supporter ✭, #52523) [Link] (1 responses)

That's actually not at all a problem. CPUs talk with DRAM through a memory controller, and it can already change the DRAM frequency.

Top-tier memory management

Posted May 30, 2021 12:29 UTC (Sun) by flussence (guest, #85566) [Link]

It's *possible*, but at present it also sounds like an incredibly niche feature for a few extra MHz that'd get shot down by manufacturers just telling users to not use mismatched RAM sticks.

This idea isn't too far from how old CPUs had independent functional units for x87/SSE/3DNow. I've heard urban legends about clever asm programmers wringing a few percent more speed out of those, but it wasn't a party trick worth spending silicon on in the long run.

Top-tier memory management

Posted May 30, 2021 10:30 UTC (Sun) by willy (subscriber, #9762) [Link]

While that sounds appealing, you're really just giving up a lot of bandwidth. If you have N sticks of RAM, you want to let the CPU put cache line L on stick L % N.

What you're proposing would put pages A-B on stick 0, B-C on stick 1, etc. It's like choosing concatenation instead of RAID 0.