Restricted DMA

It is really a matter of how far you want to go on the other side. The nice solution with what is being proposed here is that this is the bottom layer that is responsible for controlling the DMA addresses handed to an arbitrary driver, and this is located right above the driver itself. This works with a WLAN driver, but also with NVMe, Ethernet, FPGA, literally anything that uses the DMA-API if you wanted.

In the case of networking/WLAN you have socket buffers you want to transmit that are coming from user-space that are scattered in virtual and physical address space and you need to shove them through a restricted region of DRAM from which the PCIe bridge is allowed to read and write from. Bounce buffering is pretty much the only way for that direction of transfers. For receiving buffers the OS needs to allocate data buffers for the WLAN chips to put data into, so you can allocate from the restricted DMA region already and avoid the bounce buffering in that case.