Some unlikely 2021 predictions

Posted Jan 10, 2021 11:14 UTC (Sun) by jem (subscriber, #24231)
In reply to: Some unlikely 2021 predictions by Wol
Parent article: Some unlikely 2021 predictions

>Similar to the Zilog Z80, actually, except they found the bug before it shipped - how many people remember (or realised) that although it had a RightShift instruction, it didn't have a LeftShift? They deleted it from the spec because it was buggy.

You are again repeating this myth that the "Shift Left Logical" instruction is missing from the Z-80 because it was found to be buggy. Yes, the Z-80 only has three shift instructions, SLA, SRA, and SRL. The SLL instruction is missing because it is not needed: the SLA (Shift Left Arithmetic) does the same thing. Only right shifts differ between arithmetic and logical shifts.

The Z-80 has a lot more undocumented instructions, none of which are bugs. They just work the way they do because of how the processor was wired. Zilog did not intend them to be used, but also did not want to waste silicon to disable them is such a simple processor.

Some unlikely 2021 predictions

Posted Jan 10, 2021 16:59 UTC (Sun) by Wol (subscriber, #4433) [Link] (2 responses)

Okay, SLA and SLL may have the same EFFECT. But as a mathematician I like symmetry. I would document both. And the instruction code for SLL can be deduced from the other three. Except it doesn't quite do an SLL.

So the question remains. WHY did Zilog not want SLL to be used? And I hate to say it, but the *obvious* explanation is it was buggy. Especially as the instruction quite clearly existed, and *almost* worked. Three instructions is not "logically complete". And ime, not being logically complete is *asking for trouble*. What happens if an assembler-writer uses SRL, and then also uses SLL because it's the logically obvious instruction? PEOPLE DON'T READ SPECS - THEY JUMP TO CONCLUSIONS, and it's very likely people will just assume SLL exists.

(I'm aware there was a whole bunch of 16-bit instructions that happily worked on pairs of 8-bit registers but weren't documented, and also I think 8-bit instructions that worked on the 16-bit registers, but I'm not aware of any other instruction that clearly should have existed and didn't.)

Do you have any *evidence* as to why SLL wasn't documented? Or are you just looking at what happened after the chip was released, and jumping to a different conclusion from other people?

Cheers,
Wol

Some unlikely 2021 predictions

Posted Jan 10, 2021 18:39 UTC (Sun) by jem (subscriber, #24231) [Link]

>Three instructions is not "logically complete".

Tell that to CPU architects. Motorola's 6800 had the same three shift instructions as the Z-80. The 80x86 processors also only have three shift instructions. The 8086 User's Manual states: "SHL and SAL (Shift Logical Left and Shift Arithmetic Left) perform the same operation and are physically the same instruction. ARM has the LSR, LSL, and ASR. RISC-V has SRLI, SLLI, and SRAI (shift right/left logical/arithmetic immediate). MIPS? Same thing.

It is a well known fact that an arithmetic shift only differs from a logical shift when shifting "right", i.e. towards the less significant bit positions. This has been known for decades, and I doubt the engineers at Zilog were stupid when they added these instructions. So to me, the *obvious* explanation was that Zilog copied the three instructions from the Motorola 6800, and left the op code that was left unused to do what it happened to do.

What Zilog *should* have done was to do what Intel did later with the 8086: document the assembler mnemonic SLL as an alias for SLA. Or used the name SLL instead of SLA.

>And ime, not being logically complete is *asking for trouble*. What happens if an assembler-writer uses SRL, and then also uses SLL because it's the logically obvious instruction?

What *I* think is asking for trouble is when an assembler writer jumps to conclusions about the instruction set. "Ah, there is an error in the documentation, Zilog forgot to document the SLL instruction. Ok, let's use the *obvious* opcode for that." And the ship the assembler without testing it.

>Do you have any *evidence* as to why SLL wasn't documented?

Do *you* have any evidence for your original claim? That Zilog didn't intend to design their processor according to industry practice at the time, and they really intended to define four shift operations, of which two are identical? And with a stroke of extremely good luck they could just drop the SLL instruction from the documentation, when they realized at the last moment that it didn't work as expected. What are the odds of that?

Some unlikely 2021 predictions

Posted Jan 12, 2021 22:43 UTC (Tue) by floppus (guest, #137245) [Link]

But the opcode that would correspond to "SLL", despite being undocumented, does have a well-defined function: it multiplies the value by two and adds one. This is fairly well known among Z80 hackers (some people refer to this opcode as "SLIA" for "shift left inverted arithmetic", or "SL1" for "shift left and add 1".)

Sure, you can argue it'd be more parsimonious for the two opcodes to do exactly the same thing, but the undocumented function is occasionally useful to save a byte and four clock cycles.

Whether the undocumented function was intentional or not, who knows... but if it were unintentional, you'd expect that the result would be (x<<1)|(x>>7), or (x<<1)|CF, or (x<<1)|(x&1), or something even weirder, rather than (x<<1)|1.

If you simply want your assembler to emit an SLA opcode whenever you write SLL, that's an issue with the assembler, not the hardware. ;)