Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 6, 2019 21:23 UTC (Wed) by kreijack (guest, #43513)
In reply to: Generalizing address-space isolation by comio
Parent article: Generalizing address-space isolation

[Please take this post as an ironic one]

This was (is) a fantastic thread !
Some of my preferred parts:

https://groups.google.com/d/msg/comp.os.minix/wlhw16QWltI...
Andy Tanenbaum (29/01/92)
[...]
> In the meantime, RISC chips happened, and some of them are running at over
> 100 MIPS. Speeds of 200 MIPS and more are likely in the coming years.
> These things are not going to suddenly vanish. What is going to happen
> is that they will gradually take over from the 80x86 line.
[...]
> MINIX was designed to be reasonably portable, and has been ported from the
> Intel line to the 680x0 (Atari, Amiga, Macintosh), SPARC, and NS32016.
> LINUX is tied fairly closely to the 80x86. Not the way to go.
[...]

https://groups.google.com/d/msg/comp.os.minix/wlhw16QWltI...
Linus, few replies below:
[...]
> Linus "my first, and hopefully last flamefest" Torvalds

Linus, further comments below
https://groups.google.com/d/msg/comp.os.minix/wlhw16QWltI...
[...]
> Tanenbaum Writes
> > still maintain the point that designing a monolithic kernel in 1991 is
> >a fundamental error. Be thankful you are not my student. You would not
> >get a high grade for such a design :-)

> Well, I probably won't get too good grades even without you: I had an
> argument (completely unrelated - not even pertaining to OS's) with the
> person here at the university that teaches OS design. I wonder when
> I'll learn :)

BTW, when I was young I really believed that the RISC processor will be the future...

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 6, 2019 23:36 UTC (Wed) by roc (subscriber, #30627) [Link] (3 responses)

To be fair, modern x86 processors are RISC cores wrapped in an x86 decoder.

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 7, 2019 2:44 UTC (Thu) by gus3 (guest, #61103) [Link]

And Qemu is a core wrapped in a RISC decoder. Church-Turing.

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 7, 2019 19:01 UTC (Thu) by kreijack (guest, #43513) [Link] (1 responses)

> To be fair, modern x86 processors are RISC cores wrapped in an x86 decoder.
Look from the other side: the ISA is not so important; the technology has evolved to the point that the decoder is not a bottleneck anymore.

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 18, 2019 12:44 UTC (Mon) by renox (guest, #23785) [Link]

>Look from the other side: the ISA is not so important; the technology has evolved to the point that the decoder is not a bottleneck anymore.

1) only if you don't care about the power used by the decoder, it sure has not helped Intel compete against ARM in embedded CPUs..

2) ISA still matter: from memory, going from x86 to x86-64 allowed a 10% improvement in benchmarks..

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 7, 2019 12:48 UTC (Thu) by anselm (subscriber, #2796) [Link] (6 responses)

when I was young I really believed that the RISC processor will be the future

It seems to me that ARM processors aren't doing too badly these days …

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 7, 2019 14:32 UTC (Thu) by excors (subscriber, #95769) [Link] (4 responses)

Is ARM more RISCy than x86 nowadays? They both have complex instruction decoders because the instruction set doesn't match their high-performance internal architecture. E.g. some ARMs have instruction fusion for sequences like mov+movk (loading a 32-bit immediate), adrp+ldr (PC-relative load), cmp+branch, etc, then instructions get broken down again into micro-ops for execution, in a similar way to x86. The compiler-facing instruction set on ARM is more RISC-like than x86 but that seems largely irrelevant to the CPU's performance; the instruction set on both is essentially just a poorly-designed compression format for micro-ops.

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 7, 2019 23:43 UTC (Thu) by flussence (guest, #85566) [Link] (1 responses)

Isn't it technically still reduced instruction set if you have a huge pile of reduced instruction sets that happen to share a CPU? :)

(is Thumb still a thing on arm64?)

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 10, 2019 22:36 UTC (Sun) by excors (subscriber, #95769) [Link]

(There is no 64-bit version of Thumb, although ARMv8-A CPUs still support 32-bit Thumb and non-Thumb encodings so it's not saving any complexity. I guess they figured that nobody cares that much about code density outside of M-series CPUs, and those people can carry on using ARMv8-M which is 32-bit-only and Thumb-only.)

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 21, 2019 15:51 UTC (Thu) by mwsealey (subscriber, #71282) [Link] (1 responses)

Yes, Arm is more RISCy than x86 in the sense that it doesn't have LESS instructions but every instruction has less scope. RISC was never about reducing the number of possible combinations of opcodes, but to make sure that each 'instruction' was orthogonal up to the point that it remained useful. x86 has ADDs which can sign extend, load or store memory, AND NOT combined, and so on.

RISC decouples those so that if you have a need to do AND, NOT and ANDN, then you don't actually need a special instruction that can ANDN, you don't need memory operands for arithmetic if you have LDR and STR. Yes, it takes more instructions to do the same job, but in the end not a larger amount of time -- there isn't much of a case for LDR+LDR+ADD+STR taking any longer than MOV+ADD to actually execute.

Where Arm is less RISCy than academic RISC is the flexible second operand (i.e. you can shift and sign/zero extend inputs) which is definitely a convenience for code density. I don't think there was any consideration for 'complex decode logic' in Arm, the point was to take advantage of registers and being able to compartmentalize your memory accesses (because memory bandwidth is always bad).

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 21, 2019 15:59 UTC (Thu) by TomH (subscriber, #56149) [Link]

Hate to disappoint you but ARM has BIC which is really ANDN with a different name ;-)

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 7, 2019 18:58 UTC (Thu) by kreijack (guest, #43513) [Link]

> It seems to me that ARM processors aren't doing too badly these days …

In '90, the Acorn archimedes (one of the first arm processor that I remember) was a lot faster than the 386 (in terms of 1:2 and more). At the time the ARM was a younger processor than the x86 so the expectation was bright future for this kind of CPU. In fact after these years, every new CPU was a RISC one.

Now the ARM has yes a batter ratio power/watt; but the absolute maximum power of an ARM cpu is lesser or at most equal to an x86.

The x86 technology has evolved at the point that the decoder is not more the bottleneck. So the ISA doesn't matter anymore.

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 10, 2019 16:51 UTC (Sun) by jezuch (subscriber, #52988) [Link] (1 responses)

BTW, I have recently learned that human (natural) languages have a deep parallel to the CISC/RISC split. Some have simple syllabes that can be pronounced quickly, others have complex syllabes that take more time to articulate. But the end result is that when you measure information content over time, all languages have basically the same throughput of around 40 bps. So perhaps this is also what happened with RISC: yes, you could execute instructions faster, but this was completely offset by the fact that you needed more of them to do the same thing.

I wonder if the languages with complex syllables are also just fronts for a language with much simpler syllabes underneath, though ;)

Tanenbaum and Torvalds [was Generalizing address-space isolation]

Posted Nov 11, 2019 18:17 UTC (Mon) by rgmoore (✭ supporter ✭, #75) [Link]

My impression is that a big part of what happened was that the RISC vs CISC battle took place when raw computing power was the main limit on how fast a computer could accomplish things, so there was a serious issue of whether it was better to have many small operations with high clock speed or fewer bigger operations with a slower clock speed. But what's happened since then is that processors have outstripped the rest of the system to the point that instruction set complexity is no longer where the action is. Instead, the limit on the computer is how fast and efficiently you can get instructions and data to it. That means the big battle is now things like how big your cache is and how cleverly you use it, how you can minimize RAM latency, and whether you can avoid backtracking in a deep pipeline by using speculative execution.