Grand Schemozzle: Spectre continues to haunt

Posted Aug 13, 2019 10:26 UTC (Tue) by farnz (subscriber, #17727)
In reply to: Grand Schemozzle: Spectre continues to haunt by k8to
Parent article: Grand Schemozzle: Spectre continues to haunt

FWIW, Itanium's design assumed two things would be true in the future, and would not have suffered from Spectre problems because it didn't have hardware speculation:

Memory throughput and cache size increased far in excess of latency; this would have ensured that the large instructions (128 bits for a bundle of 3 instructions) were not a performance penalty, as the I$ would have held a large number of bundles ready to execute, and the limiting factors would have been instruction group size, and software speculation instructions.
Hardware speculation introduced more problems than it solved, and software driven speculation was the way forward - thus Itanium's explicit speculation and advanced loads, combined with hardware support for both handling loops as prologue, kernel and epilogue and register rotation to indicate parallelism in tight loops.

As reality turned out, though, memory throughput didn't increase massively compared to latency (DDR beat Rambus), and hardware speculation turned out to be a far better use of silicon space than bigger caches. Not only that, but hardware speculation actually worked well enough that even the minimal software speculation AMD64 supports (the PREFETCHx family of instructions) was largely useless - most of the time, hardware prefetching and speculation beats manual prefetching.