Load/Store tearing in this day and age?

Posted Jul 16, 2019 22:58 UTC (Tue) by excors (subscriber, #95769)
In reply to: Load/Store tearing in this day and age? by pr1268
Parent article: Who's afraid of a big bad optimizing compiler?

In this day and age, we still use chips and CPU architectures that were designed in a previous day and age, because they're widely available and well supported and (most importantly) cheap. They might not support misaligned loads (because that's a lot of hardware complexity, which was an issue in olden times), and if the compiler isn't certain that a load will be aligned (e.g. it's reading a field from an __attribute__((packed)) struct, which are pretty common in Linux) it'll have to read individual bytes.

Load/Store tearing in this day and age?

Posted Jul 17, 2019 6:58 UTC (Wed) by PaulMcKenney (✭ supporter ✭, #9624) [Link]

All good points! Plus modern CPUs often have store-immediate instructions with restricted-size immediate values, which can tempt the compiler to emit a series of store-immediate instructions for a larger store. As noted in the article, this is not a theoretical scenario.

Load/Store tearing in this day and age?

Posted Jul 18, 2019 4:21 UTC (Thu) by ncm (guest, #165) [Link]

It is very, very common on x86 for a value to straddle cache lines, which the hardware necessarily splits. An atomic that straddles cache lines presents the memory hardware a messy and typically slow job -- if you cared, you would have aligned! -- possibly even involving a kernel trap on simpler hardware.

On x86 they devote another few million transistors for each case to help avoid what would be a kernel trap. All the extra transistors strengthen Intel's (and, lately, AMD's and Samsung's) competitive position vs cheaper hardware. It's not free, because that enables a monopoly or oligopoly that may then extract rent or (worse) limit your choices.

In the US, only the former is ever considered actionable harm, despite the law recognizing both. It is artificially difficult to demonstrate the latter, where logically it should instead be assumed.

So, exercising care with alignment affords you more choice in hardware that can run your code fast enough, and safely, which might also enable saving money, too, and also power and heat, because those millions of transistors burn power.