| From: |
| Yash Shah <yash.shah-AT-sifive.com> |
| To: |
| linux-riscv-AT-lists.infradead.org, devicetree-AT-vger.kernel.org, palmer-AT-sifive.com |
| Subject: |
| [PATCH v2 0/2] L2 cache controller support for SiFive FU540 |
| Date: |
| Thu, 2 May 2019 16:04:51 +0530 |
| Message-ID: |
| <1556793293-21019-1-git-send-email-yash.shah@sifive.com> |
| Cc: |
| paul.walmsley-AT-sifive.com, linux-kernel-AT-vger.kernel.org, aou-AT-eecs.berkeley.edu, mark.rutland-AT-arm.com, robh+dt-AT-kernel.org, sachin.ghadi-AT-sifive.com, Yash Shah <yash.shah-AT-sifive.com> |
| Archive-link: |
| Article |
This patch series adds an L2 cache controller driver with DT documentation
for SiFive FU540-C000.
These two patches were initially part of the patch series:
'L2 cache controller and EDAC support for SiFive SoCs'
https://lkml.org/lkml/2019/4/15/320
In order to merge L2 cache controller driver without any dependency on EDAC,
the L2 cache controller patches are re-posted separately in this series.
The patchset is based on Linux 5.1-rc2 and tested on HiFive Unleashed
board with additional board related patches needed for testing can be
found at dev/yashs/L2_cache_controller branch of:
https://github.com/yashshah7/riscv-linux.git
Change history:
v2
- Mention the valid values for cache properties in DT documentation
- Remove the unnecessary property 'reg-names'
- Add "cache" to supported compatible string property
- Remove conditional checks from debugfs functions in sifive_l2_cache.c
Yash Shah (2):
RISC-V: Add DT documentation for SiFive L2 Cache Controller
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive
SoCs
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 +++++
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/sifive_l2_cache.c | 221 +++++++++++++++++++++
3 files changed, 273 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
create mode 100644 arch/riscv/mm/sifive_l2_cache.c
--
1.9.1
