Semantics of MMIO mapping attributes across architectures

Posted Nov 3, 2018 15:46 UTC (Sat) by matthijs (guest, #128389)
Parent article: Semantics of MMIO mapping attributes across architectures

"Weakly ordered systems must therefore insert whatever memory barriers are required to enforce this ordering."

Good luck with that, no such barrier exists on any ARM-based SoC I'm familiar with. You can easily force in-flight writes to land by doing a read to the same device, but there's no way to do this globally for writes to all devices.