Kernel support for control-flow enforcement

Posted Jun 26, 2018 2:55 UTC (Tue) by mtaht (subscriber, #11087)
Parent article: Kernel support for control-flow enforcement

It is probably hopeless for me to point once again at the mill cpu design, which has
has a segmented and inaccessible stack, no register rubble, and a PLB good to the byte + a TLB.

https://millcomputing.com/docs/security/

spectre vs the mill: https://millcomputing.com/white-papers/

No matter if the mill is never funded and built, there are many ideas left in it that I hope will see
incremental adoption in other cpus.

Kernel support for control-flow enforcement

Posted Jun 26, 2018 5:20 UTC (Tue) by alison (subscriber, #63752) [Link] (3 responses)

Has millcomputing.com ever communicated with the RISC-V folks?

We all know what TLB is, but PLB?

Kernel support for control-flow enforcement

Posted Jun 26, 2018 6:15 UTC (Tue) by cpitrat (subscriber, #116459) [Link]

Processor Local Bus I guess ?

Kernel support for control-flow enforcement

Posted Jun 26, 2018 11:11 UTC (Tue) by renox (guest, #23785) [Link]

> Has millcomputing.com ever communicated with the RISC-V folks?

Why would they? The Mill guys are building a set of patent to licence, I doubt that they're interested in helping a "free ISA" CPU.

Kernel support for control-flow enforcement

Posted Jun 26, 2018 13:12 UTC (Tue) by farnz (subscriber, #17727) [Link]

In the context of Mill, it's "Protection Lookaside Buffer" - like a TLB, but no translation, just read/write/execute permissions.