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6th RISC-V Workshop Proceedings

6th RISC-V Workshop Proceedings

Posted Jun 20, 2017 0:57 UTC (Tue) by ttelford (guest, #44176)
In reply to: 6th RISC-V Workshop Proceedings by XERC
Parent article: 6th RISC-V Workshop Proceedings

The big thing is that RISC-V is a more modern version of the DLX processor - which is literally _the_ textbook processor design. Practically every engineer who has taken a class on CPU design implemented the DLX.

RISC-V is not much of a leap from that.

So the first problem is that the design is very similar to a design virtually everyone in the field already knows.

The second problem is That RISC-V is simple/elegant enough it doesn't take a world-class engineer to understand it. It can easily replace DLX as the textbook design.

The third problem is that fully synthesizable and open source implementations of RISC-V exist already. If you have $100 you can get an FPGA and program it to be a RISC-V.

The fourth problem is that other large companies are already planning on using RISC-V going forward. For example, NVIDIA plans on using it to replace a management component in its GPU's.


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