Controlling access to the memory cache

They won't stop at simple cache partitioning tho. As I pointed out during the session concerned, all Intel are doing here is exposing the underlying cache slices already on the SoC. What they wouldn't go into during the session is the something they indirectly highlighted in the metrics presented: there's an obvious next step beyond the cache that is needed to do this right. Anyone paying attention will see it, not everyone will then realize what should actually be done. Obviously Intel did, since my question leading in that direction was deflected with "I am not authorized to answer that", which was all I wanted to know at the time.