A look at The Machine

Posted Aug 30, 2015 1:21 UTC (Sun) by mathstuf (subscriber, #69389)
In reply to: A look at The Machine by gioele
Parent article: A look at The Machine

Ooh, Mill is going to shake things up quite a bit here. Four reserved bits: one for use in implementing fork (apparently used to flag relative versus absolute…which hints that maybe the hardware representation is all relative addressing) and three for use by garbage collectors. Sixty remaining address the (flat) memory space. Casting between pointer and int is an instruction (which can presumably return NAR) to make sure you don't muck with the bits.

A look at The Machine

Posted Aug 30, 2015 22:54 UTC (Sun) by keithp (subscriber, #5140) [Link] (1 responses)

At least limited virtual address space is cheaper to hack around than limited physical address space. Swapping virtual to physical mappings is something the cache system understands, while swapping physical to device mappings makes the cache system very unhappy.

Just give us enough bits to address every particle in the universe and we'll be happy, right?

A look at The Machine

Posted Aug 30, 2015 23:15 UTC (Sun) by mathstuf (subscriber, #69389) [Link]

Well, with pointers being distinct entities from an integer representation, I imagine one could spec a Mill processor with 128 bit pointers so you'd have 124 (or 120 to expand the GC bits some) bits of address.

Looking back at the slides[1], it appears that there is virtual memory addressing, but there is only one address space. This allows them to put the TLB behind the cache (slide 52). Not sure if that would change things for The Machine.

[1]http://millcomputing.com/docs/memory/

A look at The Machine

Posted Sep 4, 2015 18:39 UTC (Fri) by adler187 (guest, #80400) [Link] (1 responses)

The IBM i (ne AS400/Systemi/etc) MI architecture has been using 128-bit pointers since the 80s and does similar things to distinguish pointers. There are many different pointer types. One is a Space Pointer, which points to a MI space object (a memory region up to 16MiB - 1 page) that can be used for storing data. The bottom 64-bits are the actual 64-bit machine pointer and the top 64-bits are are 0 except for the top bit used to indicate it's a space pointer. If the machine ever goes to a CPU with a larger address space (as has already happened in the 90s moving from 48-bit custom CISC to 64-bit POWER), more bits can be used for the address (I don't know exactly how many bits are reserved for type distinction, though).

The MI architecture has special instructions for manipulating pointers, which prevent casting back and forth between int and if you try it, the tag bit will become unset by the hardware and attempting to dereference the pointer will cause a segmentation fault. This is similar to the CHERI CPU: https://lwn.net/Articles/604298/, though CHERI differs in that it has pointers and "capabilities" and you have to opt-in to capabilities, so applications that assume pointer == long continue to work, but you can get better protection by using capabilities - on IBM i there is no such luck, you have to update your application.

A look at The Machine

Posted Sep 11, 2015 12:12 UTC (Fri) by mathstuf (subscriber, #69389) [Link]

It's nice to know that such problems have been dealt with before. However the set of software which has been exposed is, I suspect, very different for the MI versus the Mill's targets.