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Supporting filesystems in persistent memory

Supporting filesystems in persistent memory

Posted Sep 4, 2014 14:26 UTC (Thu) by etienne (guest, #25256)
In reply to: Supporting filesystems in persistent memory by dgc
Parent article: Supporting filesystems in persistent memory

> That means PCIe based devices such as NVMe storage as well as NVDIMMs that you plug into normal ddr3/ddr4 slots.

I am not sure both types can be treated the same way.
- PCIe devices are hot-plug with sufficiently good hardware.
- PCIe devices are better accessed with DMA, because then the length of the transfer is clearly known by the hardware before the start of the PCIe transaction (one PCIe transaction to transfer 4096 bytes versus a lot of transactions, one per cacheline or one per assembly instruction)
- I am not sure memory caching is easy to enable on PCIe mapped memory, there is plenty of small details there...

Also, are there conditions where a modification of the page-cache are not sent to the media, for instance a modified memory mapped file receiving a revoke system call?


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Supporting filesystems in persistent memory

Posted Sep 5, 2014 13:32 UTC (Fri) by marcH (subscriber, #57642) [Link] (1 responses)

> I am not sure memory caching is easy to enable on PCIe mapped memory, there is plenty of small details there...

Like for instance? I naively thought it was MTRR and done.

Supporting filesystems in persistent memory

Posted Sep 8, 2014 10:43 UTC (Mon) by etienne (guest, #25256) [Link]

> > I am not sure memory caching is easy to enable on PCIe mapped memory, there is plenty of small details there...
>
> Like for instance? I naively thought it was MTRR and done.

If your processor support MTRR (most of them, but maybe do not crash if not), then you can use them - problem is their number is limited and their size/alignment is a bit strict.
On newer processor you shall use PATs (http://en.wikipedia.org/wiki/Page_attribute_table).
But the problem I was thinking of is that the PCIe connection to your persistent memory device may include PCIe bridges, and that bridge may have a different "Cache Line Size", its memory base address may not include the "Prefetchable" bit (see PCI specs) and few other stuff like that (like error recovery) due to PCI history...


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