MCS locks and qspinlocks
MCS locks and qspinlocks
Posted Mar 12, 2014 11:42 UTC (Wed) by corbet (editor, #1)In reply to: MCS locks and qspinlocks by martinfick
Parent article: MCS locks and qspinlocks
They cannot be preempted by the scheduler, only by interrupts. So they have to be protected against nested calls in interrupt handlers, but that is already true of spinlocks.
Posted Mar 12, 2014 13:05 UTC (Wed)
by martinfick (subscriber, #4455)
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Posted Mar 12, 2014 13:59 UTC (Wed)
by rriggs (guest, #11598)
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Posted Mar 12, 2014 23:04 UTC (Wed)
by james (subscriber, #1325)
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What I'm not sure about is how often this situation will arise in practice. Obviously, you have to have a lock with at least two CPUs waiting for the situation to arise, and an interrupt being handled on the wrong CPU at just the wrong time. It looks like this is sufficiently infrequent that the performance hit when this happens is dwarfed by the performance benefits of the technique, but it would probably be a good idea to retry the benchmark on a machine subject to a network storm.
Posted Mar 13, 2014 3:15 UTC (Thu)
by martinfick (subscriber, #4455)
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I wonder about that since these locks are meant for highly contentious locks!
Posted Mar 13, 2014 14:30 UTC (Thu)
by raven667 (subscriber, #5198)
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Posted Mar 13, 2014 11:23 UTC (Thu)
by dvrabel (subscriber, #9500)
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Posted Mar 13, 2014 15:55 UTC (Thu)
by andresfreund (subscriber, #69562)
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Preemtion is disabled appropriately during spinlock acquiration IIRC.
Posted Aug 23, 2024 12:53 UTC (Fri)
by 301043030 (guest, #172920)
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Posted Mar 13, 2014 9:58 UTC (Thu)
by dgm (subscriber, #49227)
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MCS locks and qspinlocks
MCS locks and qspinlocks
If I'm reading this correctly (and it's quite possible I'm not), the scenario would be something like:
MCS locks and qspinlocks
Then CPU3 is still waiting for CPU2 to release the lock, which it won't do until it has returned from its interrupt handling and done whatever needed to be protected by the lock. With conventional spinlocks, CPU3 would have obtained the lock and could be doing something productive while CPU2 was still handling the interrupt.
MCS locks and qspinlocks
MCS locks and qspinlocks
MCS locks and qspinlocks
MCS locks and qspinlocks
> CPU2 tries to get the same lock, fails, and becomes next in line;
> CPU3 tries to get the same lock, fails, and becomes second in line;
> CPU2 is pre-empted by an interrupt;
> CPU1 releases the lock;
MCS locks and qspinlocks
MCS locks and qspinlocks