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LC-Asia: Facebook contemplates ARM servers

LC-Asia: Facebook contemplates ARM servers

Posted Mar 15, 2013 1:17 UTC (Fri) by butlerm (subscriber, #13312)
In reply to: LC-Asia: Facebook contemplates ARM servers by bronson
Parent article: LC-Asia: Facebook contemplates ARM servers

Each core on an eight core processor gets 1/8 of the memory bus already. If you have non-SMP cores, what is the difference? The most obvious one is if each core is less powerful you better make sure that your application can use all of them. If you are memory bandwidth constrained more cores aren't going to help, but they aren't going to hurt very much either.

An active market for processors with up to sixteen x86 processor cores certainly suggests that devices with sixteen or even thirty two smaller, somewhat lower clocked cores isn't out of line, provided you are dealing with applications that work well on a horizontally scaled, non-SMP basis. Not workstations, servers.

Cache coherency doesn't scale. That is why companies like Facebook and Google use racks of thousands of relatively lightweight servers in the first place, instead of hundred processor NUMA setups. Going to non-SMP cores on the same silicon substrate is the next logical step in that evolution. For any sufficiently large scale application, SMP is a crutch, and a power hungry, expensive one at that.


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LC-Asia: Facebook contemplates ARM servers

Posted Mar 15, 2013 1:43 UTC (Fri) by dlang (guest, #313) [Link] (1 responses)

you can't just connect processors to the memory bus, you need to setup some form of arbitration between them.

you can create systems with lots of cores, but it's not easy, it's not cheap, and it's not low power.

There's a lot more to making a non SMP system than just throwing cores on a memory bus.

LC-Asia: Facebook contemplates ARM servers

Posted Mar 15, 2013 5:45 UTC (Fri) by butlerm (subscriber, #13312) [Link]

It's certainly wouldn't be trivial, but as long as the power required per core doesn't go up, you would come out far ahead of any kind of cache coherent design. Large scale applications can't rely on cache coherency, and so they don't. At some point it is just a waste of silicon.


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