Race-to-idle

Posted Jun 14, 2012 9:08 UTC (Thu) by ttonino (guest, #4073)
Parent article: A big.LITTLE scheduler update

Race-to-idle was introduced by Intel. Intel has a high-leakage process and agressive sitch off of components in idle, making race-to-idle a good strategy for Intel hardware.

That is also why Intel needs the deeper sleep states as compared to (at least older SOI) AMD chips.

I think it needs to be figured out on a per-device basis. It is dependent on chip architecture (what gets switched off when) and on process/manufacture (how much leakage is there at the lowest voltage levels).

Also important: how often does one witch on and off, and how much power does that take. Emptying a cache to memory is not free.

Race-to-idle

Posted Jun 14, 2012 12:46 UTC (Thu) by yaap (subscriber, #71398) [Link] (1 responses)

You're right there's some implementation variations. This said, leakage becomes nasty even on LP processes nowadays. It used to be the case that clock gating could be sufficient, but from 40nm downward (even in 40LP, the low-power / low leakage variant) for good performance you want power gating for long durations. So the notion of race to idle will apply to most systems, and I can testify it applies to embedded SoCs very (VERY ;) far from Intel CPUs.

There will still be variations in how long is needed to justify the cost of mode changes, and what are the operating points available for DVFS (dynamic voltage and frequency scaling). But this may be handled as configuration.

Race-to-idle

Posted Jun 14, 2012 17:23 UTC (Thu) by PaulMcKenney (✭ supporter ✭, #9624) [Link]

One way to reduce leakage current is to switch from a big CPU to a LITTLE CPU.