Intel unveils 48-core cloud computing silicon chip (BBC)

I think the lack of cache consistency is very interesting. The slides in
PC Perspective mention "page-level memory consistency". I would like to
know more about what this means and how they intend for systems software to
manage the memory coherency. I'm wondering how much effort would be
required to get a kernel / hypervisor to run across all of the nodes in the
system. There must be some plan as to how OS instances will get in there!

Since this is not a cache coherent architecture, the kernel's approach of
using shared data structures isn't going to Just Work. But there is a
single shared memory space so maybe there is a workaround ... disable
caches on shared data structures maybe (surely that'll hose performance,
though). The fact that performance for kernel-intensive stuff might not
matter so much if you're just running virtual machines on all the nodes, I
guess, so long as KVM can make do with mostly local resources (and for any
IO with the VM, the page-level coherency can easily be explicit, I'd hope).

Should be really interesting to see what Intel come up with on this.