Intel unveils 48-core cloud computing silicon chip (BBC)

Posted Dec 3, 2009 17:48 UTC (Thu) by clugstj (subscriber, #4020)
Parent article: Intel unveils 48-core cloud computing silicon chip (BBC)

No offense to the BBC, but is this really where we should be getting tech news? They feel the need to explain what a transistor is!

Intel unveils 48-core cloud computing silicon chip (BBC)

Posted Dec 3, 2009 18:01 UTC (Thu) by sbergman27 (guest, #10767) [Link] (2 responses)

Yeah, but this monster has 27 million of those little switching thingies per core.

Intel unveils 48-core cloud computing silicon chip (BBC)

Posted Dec 3, 2009 18:15 UTC (Thu) by jsatchell (guest, #6236) [Link] (1 responses)

It means each node is roughly the complexity of a P4, or maybe a P3 and a decent cache.

I can't imagine what they have done about package bandwidth - assuming all these CPUs want to access main memory. If they are just going to run benchmarks by themselves, there will be no problem.

Intel unveils 48-core cloud computing silicon chip (BBC)

Posted Dec 3, 2009 18:49 UTC (Thu) by Trelane (subscriber, #56877) [Link]

It's a NUMA SoC with 96MB onboard memory. Interestingly, each core has 2MB cache... ;)

*removes tongue from cheek.

More info linked from ... Slashdot!?

Posted Dec 3, 2009 19:01 UTC (Thu) by MarkWilliamson (guest, #30166) [Link] (1 responses)

In what is surely a sign of the End Times ;-) Slashdot has provided a link
that I think others here will find informative: http://www.pcper.com/article.php?aid=825

The original Slashdot story is here:
http://hardware.slashdot.org/story/09/12/02/215207/Intel-...
Processor

Amongst other things, the article notes that each node is dual core, so
there are 24 processing nodes on the chip. There are several memory
controllers. Cache coherency (between nodes, I assume) is not handled by
hardware - a bit of a departure for Intel.

As a result of these design decisions, one thing which immediately occurred
to me was that the design might be useful for partitioning into smaller
virtual machines, each of which has its own dedicated memory and doesn't
need to worry about cache coherency. The VMM layer would handle any
explicit coherency control when required. Interestingly, the BBC article
suggests that Intel are talking about running many OS instances on a single
chip so I guess this might be what they are really thinking of.

I wonder what pain would be involved in getting a commodity OS such as
Linux to span the nodes in the system by managing software cache coherency.
Intel must have at least considered that, I'd have thought...