IBM details Blue Gene supercomputer (News.com)

This is nitpicking regarding processor development, but this is why all you fellows who skipped classes on Digital Design or Processor Design are a bit ... uninformed confusing hype (the amount of software) with performance (amount of bytes processed per cycle).

What about people who are a bit ... uninformed confusing performance (amount of work you can get done per second) with bus width or register width (32-bit versus 64-bit etc)?

History: When the IBM Jr. was 8 bits; the Mac was 32 bits.

Heh, that depends on what definition of "bits" you use. The PCjr memory bus was 8 bits wide, but the CPU registers were 16-bit, and memory addressing was 20-bit. The Mac had (I think) 24-bit memory addressing, 32-bit registers, and either 16- or 32-bit memory bus - I can't remember.

But historical perspective is mostly useless when evaluating a computing platform today. Amiga fans are fond of saying "yeah, but the Amiga did that back in 1987" - but it is no longer 1987, so it doesn't really matter.

Current: Most PCs aren't at 64 bits yet; the Mac is already at 128 bit -- NOW in its G4 Processor incarnations.

Once again, by what definition of "bits"?

• General-purpose register size? I believe the G4 is still a ppc32, not a ppc64. (The Power4, which will apparently be used in next-gen Macs, is a ppc64.)
• Memory addressing? Ditto - and the Pentium 4 is actually 36-bit, although it's done in a kludgy way, so PAE (36-bit mode) is not really useful unless you actually have more than 4 GB of memory.
• Data bus width? The Pentium introduced a 64-bit memory bus back in 1993; some RS/6000s use 128 bits, but I don't know if Macs do; and the issue is clouded by different memory bus speeds. (RAMBUS, for example, is narrow but runs at a much higher clock rate.)
• Floating point register size? The Intel x86 has used both 64- and 80-bit floating point since the beginning of time. PPC specifies 64-bit.
• Special-purpose registers? I'm not sure what the Altivec offers, but the PC equivalents (MMX, 3DNow!, SSE, SSE2) work on 8- through 64-bit quantities and can process multiple of these at a time. I believe Altivec handles 128 bits at a time, but I don't know how big each datum is (probably 32- or 64-bit).

Now ask what "work" is being done? Or will more work be done with 16, 32, 64 or 128 bits? When you answer that then you'll understand why in serious mission critical work when you need every possible accurate digit to tell you a real answer for a real problem people invariably go RISC or something even "above" that.

Red herring. What "serious mission critical work" are you talking about? In fields like CFD and FEA, it's much more important to have 64-bit IEEE-compliant floating point operations than to have "all the accuracy you can possibly get". You want results that are repeatable on different runs, and on different platforms - which is what the IEEE spec gives you. For business logic apps (databases etc), you want a 64-bit address space - thus, the Opteron, Power4, IA64, or traditional Unix platforms like SPARCv9 or MIPS-4. Applications that actually want 128-bit quantities (either int or fp) seem to be very few and far between.

Completeness in science is always recognized by the astute as Beauty, and this is exactly where many will grieve; pcs are many things, but none are beautiful in form or function or production.

Yet, on the other hand, there is the curious engineering phenomenon of something that looks horrible but happens to work very well. One is reminded of the well-known quote about the Ethernet architecture: "It works much better in practice than in theory." You read about CSMA/CD, and it all sounds like a horrible hack - but it works so well than Ethernet stomped out all of its major competition long before the technology advanced to the point where CSMA/CD is no longer needed.

Just remember: sometimes Beauty means the design was well-thought-out and of high quality; other times, it just means they spent too much money on case design and not enough on real R&D.