Add Network Subsystem (NSS) clock controller support for IPQ5424 SoC
From: | Luo Jie <quic_luoj-AT-quicinc.com> | |
To: | Bjorn Andersson <andersson-AT-kernel.org>, Michael Turquette <mturquette-AT-baylibre.com>, Stephen Boyd <sboyd-AT-kernel.org>, "Varadarajan Narayanan" <quic_varada-AT-quicinc.com>, Rob Herring <robh-AT-kernel.org>, "Krzysztof Kozlowski" <krzk+dt-AT-kernel.org>, Conor Dooley <conor+dt-AT-kernel.org>, "Anusha Rao" <quic_anusha-AT-quicinc.com>, Devi Priya <quic_devipriy-AT-quicinc.com>, Manikanta Mylavarapu <quic_mmanikan-AT-quicinc.com>, Georgi Djakov <djakov-AT-kernel.org>, Philipp Zabel <p.zabel-AT-pengutronix.de>, Richard Cochran <richardcochran-AT-gmail.com>, Konrad Dybcio <konradybcio-AT-kernel.org> | |
Subject: | [PATCH v7 00/10] Add Network Subsystem (NSS) clock controller support for IPQ5424 SoC | |
Date: | Tue, 14 Oct 2025 22:35:25 +0800 | |
Message-ID: | <20251014-qcom_ipq5424_nsscc-v7-0-081f4956be02@quicinc.com> | |
Cc: | <linux-arm-msm-AT-vger.kernel.org>, <linux-clk-AT-vger.kernel.org>, <linux-kernel-AT-vger.kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski-AT-linaro.org>, <devicetree-AT-vger.kernel.org>, <linux-pm-AT-vger.kernel.org>, <netdev-AT-vger.kernel.org>, <quic_kkumarcs-AT-quicinc.com>, <quic_linchen-AT-quicinc.com>, <quic_leiwei-AT-quicinc.com>, <quic_pavir-AT-quicinc.com>, <quic_suruchia-AT-quicinc.com>, Luo Jie <quic_luoj-AT-quicinc.com>, Konrad Dybcio <konrad.dybcio-AT-oss.qualcomm.com> | |
Archive-link: | Article |
The NSS clock controller on the IPQ5424 SoC provides clocks and resets to the networking related hardware blocks such as the Packet Processing Engine (PPE) and UNIPHY (PCS). Its parent clocks are sourced from the GCC, CMN PLL, and UNIPHY blocks. Additionally, register the gpll0_out_aux GCC clock, which serves as one of the parent clocks for some of the NSS clocks. The NSS NoC clocks are also enabled to use the icc-clk framework, enabling the creation of interconnect paths for the network subsystem’s connections with these NoCs. The NSS clock controller receives its input clocks from the CMN PLL outputs. The related patch series which adds support for IPQ5424 SoC in the CMN PLL driver is listed below. https://lore.kernel.org/all/20250610-qcom_ipq5424_cmnpll-... Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- Changes in v7: - Update the commit title to use #interconnect-cells as recommended. - Collect the reviewed-by tags. - Link to v6: https://lore.kernel.org/r/20250925-qcom_ipq5424_nsscc-v6-... Changes in v6: - Remove '#interconnect-cells' from the list of required properties in the DT binding. - Add the Reviewed-by tag to the IPQ5424 DT binding patch. - Link to v5: https://lore.kernel.org/r/20250909-qcom_ipq5424_nsscc-v5-... Changes in v5: - Reorder the fixes patch "Add required "interconnect-cells" property" to the beginning of the series. - Enhance the commit message to clearly explain the necessity of the #interconnect-cells property for interconnect providers, and why there is no ABI breakage for currently supported SoC IPQ9574. - Collect the reviewed-by tags. - Link to v4: https://lore.kernel.org/r/20250828-qcom_ipq5424_nsscc-v4-... Changes in v4: - Add new, generic clock names "nss" and "ppe" in DT bindings to support the newer SoC such as IPQ5424 SoC, while retaining existing clock names for IPQ9574. - Register all necessary NoC clocks as interconnect paths. - Separate the fix for correcting icc_first_node_id into its own patch. - Separate the fix requiring the "#interconnect-cells" property for NSS clock controller node. - Update commit titles from "clock:" to "clk:" for consistency. - Update copyright to remove year as per guidelines in all driver files. - Remove the Acked-by tag from the "Add Qualcomm IPQ5424 NSSNOC IDs" patch" as the new NOC IDs are added. - Link to v3: https://lore.kernel.org/r/20250710-qcom_ipq5424_nsscc-v3-... Changes in v3: - Remove frequency suffix from clock names for PPE and NSS clocks in IPQ9574 DT binding and DTS. - Update IPQ5424 DT bindings and DTS to as per new PPE and NSS clock names. - Expand the register region of IPQ5424 NSSCC to utilize the entire 0x100_000 address range, ensuring inclusion of the wrapper region. - Collect the reviewed-by tags. - Link to v2: https://lore.kernel.org/r/20250627-qcom_ipq5424_nsscc-v2-... Changes in v2: - Add new, separate clock names "nss" and "ppe" in dtbindings to support the IPQ5424 SoC. - Wrap the commit message body at 75 columns. - Fix the indentation issue in the `IPQ_NSSCC_5424` Kconfig entry. - Enhance the commit message for the defconfig patch to clarify the requirement for enabling `IPQ_NSSCC_5424`. - Link to v1: https://lore.kernel.org/r/20250617-qcom_ipq5424_nsscc-v1-... --- Luo Jie (10): clk: qcom: gcc-ipq5424: Correct the icc_first_node_id dt-bindings: clock: Add "#interconnect-cells" property in IPQ9574 example dt-bindings: interconnect: Add Qualcomm IPQ5424 NSSNOC IDs clk: qcom: gcc-ipq5424: Enable NSS NoC clocks to use icc-clk dt-bindings: clock: gcc-ipq5424: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC clk: qcom: Add NSS clock controller driver for IPQ5424 arm64: dts: qcom: ipq5424: Add NSS clock controller node arm64: defconfig: Build NSS clock controller driver for IPQ5424 .../bindings/clock/qcom,ipq9574-nsscc.yaml | 63 +- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 32 +- arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5424.c | 28 +- drivers/clk/qcom/nsscc-ipq5424.c | 1340 ++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq5424-gcc.h | 3 +- include/dt-bindings/clock/qcom,ipq5424-nsscc.h | 65 + include/dt-bindings/interconnect/qcom,ipq5424.h | 33 + include/dt-bindings/reset/qcom,ipq5424-nsscc.h | 46 + 11 files changed, 1612 insertions(+), 11 deletions(-) --- base-commit: 13863a59e410cab46d26751941980dc8f088b9b3 change-id: 20251014-qcom_ipq5424_nsscc-eebd62a31e74 Best regards, -- Luo Jie <quic_luoj@quicinc.com>