| From: |
| Randolph Lin <randolph-AT-andestech.com> |
| To: |
| <linux-kernel-AT-vger.kernel.org> |
| Subject: |
| [PATCH v7 0/5] Add support for Andes Qilai SoC PCIe controller |
| Date: |
| Mon, 13 Oct 2025 18:41:41 +0800 |
| Message-ID: |
| <20251013104146.578319-1-randolph@andestech.com> |
| Cc: |
| <linux-pci-AT-vger.kernel.org>, <linux-riscv-AT-lists.infradead.org>, <devicetree-AT-vger.kernel.org>, <jingoohan1-AT-gmail.com>, <mani-AT-kernel.org>, <lpieralisi-AT-kernel.org>, <kwilczynski-AT-kernel.org>, <robh-AT-kernel.org>, <bhelgaas-AT-google.com>, <krzk+dt-AT-kernel.org>, <conor+dt-AT-kernel.org>, <alex-AT-ghiti.fr>, <aou-AT-eecs.berkeley.edu>, <palmer-AT-dabbelt.com>, <paul.walmsley-AT-sifive.com>, <ben717-AT-andestech.com>, <inochiama-AT-gmail.com>, <thippeswamy.havalige-AT-amd.com>, <namcao-AT-linutronix.de>, <shradha.t-AT-samsung.com>, <pjw-AT-kernel.org>, <randolph.sklin-AT-gmail.com>, <tim609-AT-andestech.com>, Randolph Lin <randolph-AT-andestech.com> |
| Archive-link: |
| Article |
Add support for Andes Qilai SoC PCIe controller
These patches introduce driver support for the PCIe controller on the
Andes Qilai SoC.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
Changes in v7:
- Remove unnecessary nodes and property in DTS bindings
---
Changes in v6:
- Fix typo in the logic for adjusting the number of OB/IB windows
---
Changes in v5:
- Add support to adjust the number of OB/IB windows in the glue driver.
- Fix the number of OB windows in the Qilai PCIe driver.
- Remove meaningless properties from the device tree.
- Made minor adjustments based on the reviewer's suggestions.
---
Changes in v4:
- Add .post_init callback for enabling IOCP cache.
- Sort by vender name in Kconfig
- Using PROBE_PREFER_ASYNCHRONOUS as default probe type.
- Made minor adjustments based on the reviewer's suggestions.
---
Changes in v3:
- Remove outbound ATU address range validation callback and logic.
- Add logic to skip failed outbound iATU configuration and continue.
- Using PROBE_PREFER_ASYNCHRONOUS as default probe type.
- Made minor adjustments based on the reviewer's suggestions.
---
Changes in v2:
- Remove the patch that adds the dma-ranges property to the SoC node.
- Add dma-ranges to the PCIe parent node bus node.
- Refactor and rename outbound ATU address range validation callback and logic.
- Use parent_bus_offset instead of cpu_addr_fixup().
- Using PROBE_DEFAULT_STRATEGY as default probe type.
- Made minor adjustments based on the reviewer's suggestions.
Randolph Lin (5):
PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
dt-bindings: PCI: Add Andes QiLai PCIe support
riscv: dts: andes: Add PCIe node into the QiLai SoC
PCI: andes: Add Andes QiLai SoC PCIe host driver support
MAINTAINERS: Add maintainers for Andes QiLai PCIe driver
.../bindings/pci/andestech,qilai-pcie.yaml | 84 ++++++
MAINTAINERS | 7 +
arch/riscv/boot/dts/andes/qilai.dtsi | 106 ++++++++
drivers/pci/controller/dwc/Kconfig | 13 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-andes-qilai.c | 240 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.c | 12 +-
7 files changed, 461 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c
--
2.34.1
