| From: |
| Vincent Guittot <vincent.guittot-AT-linaro.org> |
| To: |
| chester62515-AT-gmail.com, mbrugger-AT-suse.com, ghennadi.procopciuc-AT-oss.nxp.com, s32-AT-nxp.com, bhelgaas-AT-google.com, jingoohan1-AT-gmail.com, lpieralisi-AT-kernel.org, kwilczynski-AT-kernel.org, mani-AT-kernel.org, robh-AT-kernel.org, krzk+dt-AT-kernel.org, conor+dt-AT-kernel.org, Ionut.Vicovan-AT-nxp.com, larisa.grigore-AT-nxp.com, Ghennadi.Procopciuc-AT-nxp.com, ciprianmarian.costea-AT-nxp.com, bogdan.hamciuc-AT-nxp.com, Frank.li-AT-nxp.com, linux-arm-kernel-AT-lists.infradead.org, linux-pci-AT-vger.kernel.org, devicetree-AT-vger.kernel.org, linux-kernel-AT-vger.kernel.org, imx-AT-lists.linux.dev |
| Subject: |
| [PATCH 0/4 v2] PCI: s32g: Add support for PCIe controller |
| Date: |
| Fri, 19 Sep 2025 17:58:18 +0200 |
| Message-ID: |
| <20250919155821.95334-1-vincent.guittot@linaro.org> |
| Cc: |
| cassel-AT-kernel.org |
| Archive-link: |
| Article |
The S32G SoC family has 2 PCIe controllers based on Designware IP.
Add the support for Host mode.
Change since v1:
- Cleanup DT binding
- Removed useless description and fixed typo, naming and indentation.
- Removed nxp,phy-mode binding until we agreed on a generic binding.
Default (crnss) mode is used for now. Generic binding wil be discussed
in a separate patch.
- Removed max-link-speed and num-lanes which are coming from
snps,dw-pcie-common.yaml. They are needed only if to restrict from the
the default hw config.
- Added unevaluatedProperties: false
- Keep Phys in host node until dw support Root Port node.
- Removed nxp-s32g-pcie-phy-submode.h until there is a generic clock and
spectrum binding.
- Rename files to start with pcie-s32g instead of pci-s32g
- Cleanup pcie-s32-reg.h and use dw_pcie_find_capability()
- cleanup and rename in s32g-pcie.c in addtion to remove useless check or
duplicate code.
- dw_pcie_suspend/resume_noirq() doesn't woork, need to set child device
to reach lowest state.
- Added L: imx@lists.linux.dev in MAINTAINERS
Vincent Guittot (3):
dt-bindings: PCI: s32g: Add NXP PCIe controller
PCI: s32g: Add initial PCIe support (RC)
MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver
.../devicetree/bindings/pci/nxp,s32-pcie.yaml | 131 ++++
MAINTAINERS | 4 +
drivers/pci/controller/dwc/Kconfig | 11 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-designware.h | 1 +
drivers/pci/controller/dwc/pcie-s32g-regs.h | 61 ++
drivers/pci/controller/dwc/pcie-s32g.c | 578 ++++++++++++++++++
7 files changed, 787 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-s32g-regs.h
create mode 100644 drivers/pci/controller/dwc/pcie-s32g.c
--
2.43.0
