| From: |
| Judith Mendez <jm-AT-ti.com> |
| To: |
| Judith Mendez <jm-AT-ti.com>, Nishanth Menon <nm-AT-ti.com>, Tero Kristo <kristo-AT-kernel.org>, Rob Herring <robh-AT-kernel.org>, Krzysztof Kozlowski <krzk+dt-AT-kernel.org>, Conor Dooley <conor+dt-AT-kernel.org>, Adrian Hunter <adrian.hunter-AT-intel.com>, Ulf Hansson <ulf.hansson-AT-linaro.org> |
| Subject: |
| [PATCH 0/4] Add support for AM62P SR1.2 |
| Date: |
| Tue, 05 Aug 2025 18:49:46 -0500 |
| Message-ID: |
| <20250805234950.3781367-1-jm@ti.com> |
| Cc: |
| Vignesh Raghavendra <vigneshr-AT-ti.com>, Santosh Shilimkar <ssantosh-AT-kernel.org>, <linux-arm-kernel-AT-lists.infradead.org>, <devicetree-AT-vger.kernel.org>, <linux-kernel-AT-vger.kernel.org>, <linux-mmc-AT-vger.kernel.org> |
| Archive-link: |
| Article |
This patch series adds support for the AM62P SR1.2 silicon revision by
adding logic in k3-socinfo to detect AM62P variants. Also update binding
doc to account for second register range GP_SW.
This also disables HS400 support for AM62P SR1.0 and SR1.1 in sdhci host
driver and enable by default for AM62P SR1.2.
Tested against AM62P SR1.2, SR1.1, SR1.0 and AM62X SK.
Log for AM62P SR1.2:
https://gist.github.com/jmenti/5d06c60a94104a476eda9371ab...
Judith Mendez (4):
dt-bindings: hwinfo: Add second register range for GP_SW
soc: ti: k3-socinfo: Add support for AM62P variants
mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1
arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW reg range to
chipid node
.../bindings/hwinfo/ti,k3-socinfo.yaml | 9 +-
.../dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 3 +-
drivers/mmc/host/sdhci_am654.c | 16 ++++
drivers/soc/ti/k3-socinfo.c | 82 +++++++++++++++++--
4 files changed, 98 insertions(+), 12 deletions(-)
--
2.49.0
