riscv: add initial support for hardware breakpoints
From: | Jesse Taube <jesse-AT-rivosinc.com> | |
To: | linux-riscv-AT-lists.infradead.org | |
Subject: | [PATCH 0/8] riscv: add initial support for hardware breakpoints | |
Date: | Tue, 05 Aug 2025 12:39:47 -0700 | |
Message-ID: | <20250805193955.798277-1-jesse@rivosinc.com> | |
Cc: | Paul Walmsley <paul.walmsley-AT-sifive.com>, Palmer Dabbelt <palmer-AT-dabbelt.com>, Albert Ou <aou-AT-eecs.berkeley.edu>, Alexandre Ghiti <alex-AT-ghiti.fr>, Oleg Nesterov <oleg-AT-redhat.com>, Kees Cook <kees-AT-kernel.org>, Peter Zijlstra <peterz-AT-infradead.org>, Ingo Molnar <mingo-AT-redhat.com>, Arnaldo Carvalho de Melo <acme-AT-kernel.org>, Namhyung Kim <namhyung-AT-kernel.org>, Mark Rutland <mark.rutland-AT-arm.com>, Alexander Shishkin <alexander.shishkin-AT-linux.intel.com>, Jiri Olsa <jolsa-AT-kernel.org>, Ian Rogers <irogers-AT-google.com>, Adrian Hunter <adrian.hunter-AT-intel.com>, "Liang, Kan" <kan.liang-AT-linux.intel.com>, Shuah Khan <shuah-AT-kernel.org>, Jesse Taube <jesse-AT-rivosinc.com>, Himanshu Chauhan <hchauhan-AT-ventanamicro.com>, Charlie Jenkins <charlie-AT-rivosinc.com>, Samuel Holland <samuel.holland-AT-sifive.com>, Conor Dooley <conor.dooley-AT-microchip.com>, Deepak Gupta <debug-AT-rivosinc.com>, Andrew Jones <ajones-AT-ventanamicro.com>, Atish Patra <atishp-AT-rivosinc.com>, Anup Patel <apatel-AT-ventanamicro.com>, Mayuresh Chitale <mchitale-AT-ventanamicro.com>, Evan Green <evan-AT-rivosinc.com>, WangYuli <wangyuli-AT-uniontech.com>, Huacai Chen <chenhuacai-AT-kernel.org>, Arnd Bergmann <arnd-AT-arndb.de>, Andrew Morton <akpm-AT-linux-foundation.org>, Luis Chamberlain <mcgrof-AT-kernel.org>, "Mike Rapoport (Microsoft)" <rppt-AT-kernel.org>, Nam Cao <namcao-AT-linutronix.de>, Yunhui Cui <cuiyunhui-AT-bytedance.com>, Joel Granados <joel.granados-AT-kernel.org>, Clément Léger <cleger-AT-rivosinc.com>, Sebastian Andrzej Siewior <bigeasy-AT-linutronix.de>, Celeste Liu <coelacanthushex-AT-gmail.com>, Chunyan Zhang <zhangchunyan-AT-iscas.ac.cn>, Nylon Chen <nylon.chen-AT-sifive.com>, Thomas Gleixner <tglx-AT-linutronix.de>, Thomas Weißschuh <thomas.weissschuh-AT-linutronix.de>, Vincenzo Frascino <vincenzo.frascino-AT-arm.com>, Joey Gouly <joey.gouly-AT-arm.com>, Akihiko Odaki <akihiko.odaki-AT-daynix.com>, Ravi Bangoria <ravi.bangoria-AT-amd.com>, linux-kernel-AT-vger.kernel.org, linux-mm-AT-kvack.org, linux-perf-users-AT-vger.kernel.org, linux-kselftest-AT-vger.kernel.org | |
Archive-link: | Article |
This patchset adds initial support for hardware breakpoints and watchpoints to the RISC-V architecture. The framework is built on top of perf subsystem and SBI debug trigger extension. Currently following features are not supported and are in works: - icount for single stepping - Virtualization of debug triggers - kernel space debug triggers The SBI debug trigger extension can be found at: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/maste... The Sdtrig ISA is part of RISC-V debug specification which can be found at: https://github.com/riscv/riscv-debug-spec based off the original RFC by Himanshu Chauhan here: https://lore.kernel.org/lkml/20240222125059.13331-1-hchau... Second RFC by Jesse Taube here: https://lore.kernel.org/lkml/20250722173829.984082-1-jess... Himanshu Chauhan (2): riscv: Add SBI debug trigger extension and function ids riscv: Introduce support for hardware break/watchpoints Jesse Taube (6): riscv: Add insn.c, consolidate instruction decoding riscv: insn: Add get_insn_nofault riscv: hw_breakpoint: Use icount for single stepping riscv: ptrace: Add hw breakpoint support riscv: ptrace: Add hw breakpoint regset selftests: riscv: Add test for hardware breakpoints arch/riscv/Kconfig | 13 + arch/riscv/include/asm/bug.h | 12 - arch/riscv/include/asm/hw_breakpoint.h | 59 ++ arch/riscv/include/asm/insn.h | 132 ++- arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/processor.h | 4 + arch/riscv/include/asm/sbi.h | 33 +- arch/riscv/include/uapi/asm/ptrace.h | 9 + arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/hw_breakpoint.c | 769 ++++++++++++++++++ arch/riscv/kernel/insn.c | 165 ++++ arch/riscv/kernel/kgdb.c | 102 +-- arch/riscv/kernel/probes/kprobes.c | 1 + arch/riscv/kernel/process.c | 4 + arch/riscv/kernel/ptrace.c | 169 ++++ arch/riscv/kernel/traps.c | 11 +- arch/riscv/kernel/traps_misaligned.c | 93 +-- include/uapi/linux/elf.h | 2 + tools/include/uapi/linux/elf.h | 1 + tools/perf/tests/tests.h | 3 +- tools/testing/selftests/riscv/Makefile | 2 +- .../selftests/riscv/breakpoints/.gitignore | 1 + .../selftests/riscv/breakpoints/Makefile | 12 + .../riscv/breakpoints/breakpoint_test.c | 246 ++++++ 24 files changed, 1657 insertions(+), 191 deletions(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c create mode 100644 arch/riscv/kernel/insn.c create mode 100644 tools/testing/selftests/riscv/breakpoints/.gitignore create mode 100644 tools/testing/selftests/riscv/breakpoints/Makefile create mode 100644 tools/testing/selftests/riscv/breakpoints/breakpoint_test.c -- 2.43.0