kmalloc

Posted Apr 13, 2025 8:17 UTC (Sun) by gmprice (subscriber, #167884)
In reply to: kmalloc by cesarb
Parent article: Management of volatile CXL devices

This has already been proposed. https://arxiv.org/pdf/2305.05033

IIRC the idea is basically you can route more CXL lanes to the chip than you can DDR, so you can get more bandwidth in exchange for latency.

Not sure I buy their assessments completely, but it's interesting I suppose.