That ignores pipelining

That ignores pipelining

Posted Feb 28, 2025 10:19 UTC (Fri) by farnz (subscriber, #17727)
In reply to: That ignores pipelining by taladar
Parent article: Building an open-source battery

That's what I was getting at when I wrote:

Where size becomes an issue is where latencies are critical - if a device is small, everything can be assumed to happen in a single clock cycle, but as the scale increases, the minimum latency also increases. You thus have an extra layer of complexity when clocks increase, because you can no longer place devices freely; you have to allow for latency issues.

As frequency increases, you quantise the possible latencies of an operation into more buckets; a signal travelling 2 cm in a typical chip takes about 0.1 nanoseconds to do that (speed of light in a silicon chip is about 2/3rds of that in a vacuum). If your clock cycle time is 1,000 nanoseconds, then it's easy to ensure that everything in your chip is at most half a cycle time away from everything else.

But if your clock cycle time is now 0.2 nanoseconds (5 GHz), you have to place the latency sensitive parts with care; you need the things that cannot wait more than 1 clock cycle to be safely under 4 cm apart at their furthest extents, because even 4cm is too far to be reliable (since logic has its own delays and required timings to meet when the signal enters and exits part of the chip). You can put things that can tolerate a 10,000 cycle delay at 5 GHz on different chips on a motherboard, since your 10,000 cycle delay is 2 microseconds, giving you about 300 meters, even as you put things that cannot tolerate more than 1 cycle latency 2 cm apart.

Note though, that this doesn't make 5 GHz impossible on a chip that's 80mm by 80mm; it just means that you have to work a lot harder on chip layout for a 5 GHz chip than you do for a 2 GHz chip of the same size.

---

to post comments