LWN: Comments on "Stuffing the return stack buffer" https://lwn.net/Articles/901834/ This is a special feed containing comments posted to the individual LWN article titled "Stuffing the return stack buffer". en-us Tue, 21 Oct 2025 11:41:49 +0000 Tue, 21 Oct 2025 11:41:49 +0000 https://www.rssboard.org/rss-specification lwn@lwn.net Stuffing the return stack buffer https://lwn.net/Articles/903579/ https://lwn.net/Articles/903579/ immibis <div class="FormattedComment"> &quot;have the time dimension part of the ISA&quot; is a rather pretentious way of saying &quot;add an instruction to flush cached microarchitectural state&quot;<br> </div> Tue, 02 Aug 2022 17:13:27 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902880/ https://lwn.net/Articles/902880/ smitty_one_each <div class="FormattedComment"> <a href="https://www.hyrumslaw.com/">https://www.hyrumslaw.com/</a> tells us that someone, somewhere, is making use off all of these behavioral aspects of the chip.<br> <p> And that is disquieting.<br> </div> Fri, 29 Jul 2022 13:48:23 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902685/ https://lwn.net/Articles/902685/ izbyshev <font class="QuotedText">&gt; CPU designer often put in "chicken bits" for disabling new microarchitectural features, in case they turn out to be buggy. </font> <p> Yeah, like <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.18.y&id=80f8a9e9d530fec6094641b96fe3e5b5acb44830">this one</a> :) Wed, 27 Jul 2022 20:53:36 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902665/ https://lwn.net/Articles/902665/ anton Actually it is somewhat surprising. CPU designer often put in "chicken bits" for disabling new microarchitectural features, in case they turn out to be buggy. You can then still sell the CPU instead of having to scrap it. And some of these chicken bits have been known to be used over the years (and probably many more were used before the CPUs were released, and the public never heard of them). <p>But when they designed this fallback from the return stack buffer to the history-based indirect branch predictor into Skylake, they apparently did not put a chicken bit for that in, probably because history-based indirect branch prediction had been present in Intel CPUs for many generations. Wed, 27 Jul 2022 15:01:52 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902549/ https://lwn.net/Articles/902549/ izbyshev <div class="FormattedComment"> <font class="QuotedText">&gt; RSB stuffing relies on retpolines for Spectre v2 mitigation. </font><br> <p> FWIW, it&#x27;s vice versa: retpolines rely on RSB stuffing to make them less broken on Skylake.<br> <p> But yeah, the general sentiment of that email is that apparently retpolines would be unsafe on Skylake even if RSB stuffing were added in all cases when the RSB might become empty.<br> <p> </div> Tue, 26 Jul 2022 14:47:10 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902548/ https://lwn.net/Articles/902548/ mss Some knowledgeable people <a href="https://lore.kernel.org/kvm/02ff6ca4-7878-e848-cb3d-af880b1bbb58@citrix.com/">already say</a> that: <blockquote> Retpoline <b>is not safe</b> on Skylake-era CPUs, and we knew this before the Spectre/Meltdown embargo broke in Jan '18. </blockquote> <br> RSB stuffing relies on retpolines for Spectre v2 mitigation. Tue, 26 Jul 2022 13:47:13 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902488/ https://lwn.net/Articles/902488/ developer122 <div class="FormattedComment"> In other words, &quot;it&#x27;s fixed until we discover otherwise&quot;<br> </div> Tue, 26 Jul 2022 00:24:05 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902351/ https://lwn.net/Articles/902351/ Paf <div class="FormattedComment"> I mean, they talk about how to make that specific operation more efficient and it could be worse, but …….. yes.<br> </div> Sun, 24 Jul 2022 23:03:24 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902346/ https://lwn.net/Articles/902346/ kenmoffat <div class="FormattedComment"> So yes, not exactly the same vulnerability, but the same mitigation. <br> </div> Sun, 24 Jul 2022 20:24:39 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902347/ https://lwn.net/Articles/902347/ Sesse <div class="FormattedComment"> So all your syscalls are now basically as expensive as you can possibly make them?<br> </div> Sun, 24 Jul 2022 20:19:35 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902341/ https://lwn.net/Articles/902341/ izbyshev <div class="FormattedComment"> I can&#x27;t find any indications of Intel CPU designers being involved in this mitigation, but from what I could understand, the newest CPUs are not affected, so, indeed, the mitigation has to work only on a known set of CPUs.<br> </div> Sun, 24 Jul 2022 18:14:24 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902340/ https://lwn.net/Articles/902340/ Paf <div class="FormattedComment"> Which seems fine, since if the CPU designers were involved, it’s probably ok for existing CPUs and fixed in future, right?<br> </div> Sun, 24 Jul 2022 17:44:50 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902339/ https://lwn.net/Articles/902339/ izbyshev And indeed, quoting the patch: <pre> + * The shift count might cause this to be off by one in either direction, + * but there is still a cushion vs. the RSB depth. The algorithm does not + * claim to be perfect and it can be speculated around by the CPU, but it + * is considered that it obfuscates the problem enough to make exploitation + * extremly difficult. </pre> Sun, 24 Jul 2022 17:18:48 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902337/ https://lwn.net/Articles/902337/ izbyshev But it's directly followed by <code>ret</code> on the fallthrough path. If the speculation window could be arbitrarily large, I don't see what would prevent CPU from simply bypassing the RSB stuffing code by taking the fallthrough path N times where N is the size of the RSB, and then still using the attacker-controlled indirect branch predictor. So it seems that this mitigation relies on a certain upper bound on the size of the speculation window. Sun, 24 Jul 2022 17:12:00 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902336/ https://lwn.net/Articles/902336/ mss <code>jz 1f</code> is not an indirect branch. Sun, 24 Jul 2022 16:06:35 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902334/ https://lwn.net/Articles/902334/ izbyshev <div class="FormattedComment"> I guess it does, and that&#x27;s why &quot;safety margin of four calls&quot; mentioned in the article is needed.<br> </div> Sun, 24 Jul 2022 14:36:07 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902323/ https://lwn.net/Articles/902323/ mss The <a href="https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html">Intel affected CPU model page</a> says that Ice Lake models are not affected by INTEL-SA-00702.<br> <br> eIBRS parts had <a href="https://lwn.net/Articles/887326/">their own vulnerability in March</a> (the relevant paper is <a href="https://www.usenix.org/system/files/sec22fall_barberis.pdf">here</a>), which apparently can also be used to mount Retbleed-style attacks. Sun, 24 Jul 2022 14:13:59 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902313/ https://lwn.net/Articles/902313/ kenmoffat I've been told that Ice Lake and later, except Alder Lake are vulnerable, and that the mitigation will also run on Alder Lake until new firmware is applied. See INTEL-SA-00702 Sun, 24 Jul 2022 11:45:49 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902312/ https://lwn.net/Articles/902312/ fw Huh. Why doesn't the CPU execute the conditional branch in <code>shlq $5, PER_CPU_VAR(__x86_call_depth); jz 1f</code> speculatively, defeating the mitigation? Sun, 24 Jul 2022 10:56:31 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902307/ https://lwn.net/Articles/902307/ petkan <div class="FormattedComment"> ... and of course big &quot;F*** you, Intel&quot; for making 3/4 of all machines that i own a rather expensive paperweight.<br> </div> Sun, 24 Jul 2022 06:42:51 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902304/ https://lwn.net/Articles/902304/ petkan <div class="FormattedComment"> If you need _real_ security it just better to not use _any_ sort of computer. ;)<br> </div> Sun, 24 Jul 2022 06:33:00 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902296/ https://lwn.net/Articles/902296/ developer122 <div class="FormattedComment"> Microcode is not all-powerful. Certain key mechanisms must be hardwired for performance reasons.<br> </div> Sun, 24 Jul 2022 00:32:04 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902292/ https://lwn.net/Articles/902292/ kenmoffat <div class="FormattedComment"> My understanding is that on intel (AMD retbleed is a different vulnerability), anything before Skylake is not affected. Certainly, my haswell claims to be not vulnerable. And recent intel (gen 10 and later) are apparently also ok, so this seems to be only for generations 6 to 9.<br> </div> Sat, 23 Jul 2022 21:42:00 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902285/ https://lwn.net/Articles/902285/ jhoblitt <div class="FormattedComment"> That isn&#x27;t surprising... even if a heroic microcode fix was possible, there is obviously a strong financial incentive to push customers towards purchasing new chips (which already have a, presumably, well validated mitigation).<br> <p> I genuinely appreciate the effort and wizardry going into this problem. I suspect many are in the position of considering risk and evaluating which hosts need retbleed mitigation... and which subset of those can&#x27;t afford a 1/3 loss of capacity. <br> <p> It is looking like the ultimate solution is either to buy more hardware to compensate for increased kernel overhead or to upgrade to Intel &quot;12th&quot; gen or newer cpus with eIBRS support? Either option is difficult with the current unprecedented lead times on IT equipment. <br> <p> Of course, I accepted delivery of 5 pallets of zen3 based servers immediately prior to the public retbleed disclosure.<br> </div> Sat, 23 Jul 2022 19:13:51 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902278/ https://lwn.net/Articles/902278/ epa <div class="FormattedComment"> ...or somehow you arrange for all the cores sharing a cache to be running code from the same protection domain at the same time. When one context switches to a different user or to the kernel, they all must.<br> </div> Sat, 23 Jul 2022 16:26:59 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902272/ https://lwn.net/Articles/902272/ Paf <div class="FormattedComment"> Specifically, at context switches. So this looks to be only truly applicable on a system where cores are entirely independent or there’s just one core. This looks like a very limited mitigation and not much applicable to the larger cores we work with. It also relies on knowing what “all micro architecture state” is - part of the steady march of these issues has been people finding things that weren’t previously recognized as “state” worthy of protecting.<br> </div> Sat, 23 Jul 2022 14:47:11 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902270/ https://lwn.net/Articles/902270/ tglx <div class="FormattedComment"> Exactly zero. If that would be feasible we would not discuss such a workaround at all.<br> </div> Sat, 23 Jul 2022 14:42:36 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902269/ https://lwn.net/Articles/902269/ Paf <div class="FormattedComment"> “ We show that the addition of a single-instruction extension to the RISC-V ISA, that flushes microarchitectural state,”<br> <p> That doesn’t sound like including the time domain…? It’s just flushing all state at certain transitions?<br> </div> Sat, 23 Jul 2022 14:41:47 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902268/ https://lwn.net/Articles/902268/ jhoblitt <div class="FormattedComment"> What are the odds that a microcode update could disable falling back on &quot;other heuristics&quot; when the RSB is exhausted?<br> </div> Sat, 23 Jul 2022 14:15:21 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902263/ https://lwn.net/Articles/902263/ mss <div class="FormattedComment"> Current CPUs are far faster than an Ivy Bridge CPU from a decade ago, even when the necessary mitigations for speculative execution vulnerabilities are enabled.<br> <p> And these mitigations can always be disabled if not applicable to one&#x27;s threat model.<br> </div> Sat, 23 Jul 2022 13:23:29 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902253/ https://lwn.net/Articles/902253/ felixfix <div class="FormattedComment"> Holy mackerel! There is nothing new under the sun!<br> <p> Waaaay back when, late 1970s, I worked on Datapoint 2200/5500/6600 8 bit computers, Datapoint&#x27;s extension of the basic 8008 into Z80 level, but different: no IX IY regs, had system/user modes, other differences.<br> <p> It also had a 16 level hardware stack with no overflow or underflow detection or warning.<br> <p> Its only interrupt was every millisecond whether you wanted it or not. Everything was polled.<br> <p> We threw in a push, push, pop, pop, to force always using 3 levels of stack, because none of our interrupt code was supposed to use more than two levels, and user code was expected to never use more than 13 levels.<br> <p> Deja vu all over again!<br> </div> Sat, 23 Jul 2022 03:39:39 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902248/ https://lwn.net/Articles/902248/ scientes The real <b>another way</b> is to have the time dimension part of the ISA: <br></br><br></br> <a href="https://arxiv.org/pdf/2005.02193.pdf">Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core</a> <br></br><br></br> Such as with this suggested new instruction, part of seL4 development. Sat, 23 Jul 2022 00:40:00 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902235/ https://lwn.net/Articles/902235/ developer122 <div class="FormattedComment"> That T430 thinkpad is feeling like a really great investment right about now.<br> </div> Fri, 22 Jul 2022 22:11:09 +0000 Stuffing the return stack buffer https://lwn.net/Articles/902227/ https://lwn.net/Articles/902227/ alonz I like that last sentence ("all we can do right now is to speculate about that"). Yeah, look where speculation has brought us&mldr; Fri, 22 Jul 2022 18:27:01 +0000