LWN: Comments on "Reworking page-table traversal"

Reworking page-table traversal

kiryl — Thu, 10 May 2018 20:54:27 +0000

8-byte entries is not enough. We already run out of bits in the entries and every new feature wants to claim one (or 15 with MKTME :P).

Why is separate roots from kernel/user useful? Is it only to protect against Meltdown-alike stuff?

Reworking page-table traversal

luto — Tue, 08 May 2018 23:53:42 +0000

There’s no need for an 8k page. All that would be needed is bigger page table chunks. 8k (i.e. two-page) directories with 8-byte entries gives 10 bits of VA per level. 12+5*10 = 62 bits. Now give separate roots for the top and bottom halves of the address space and 63 of the 64 possible bits are covered.

Intel, if you ever revamp the page table format again, here are some feature requests:

- Separate R, W, and X bits.

- Separate page table roots for the top and bottom halves of the address space. Or, even better, separate user-mode and kernel-mode page tables.

- At least one extra address space accessible with prefixes or special instructions. For example, having the stack live in a separate address space accessible only with PUSH, POP, and prefixed memory operands would be awesome.

(Hmm. There are already mostly-useless CS, SS, DS, ES, FS, and GS prefixes. Make each one refer to a separate address space. Make ES, FS, and GS be usable only at CPL0, and make CPL0 default to the ES space and CPL > 0 default to CS.)

Reworking page-table traversal

cborni — Mon, 07 May 2018 12:40:01 +0000

Yes we have 5. The tricky thing is that the format of the page tables differ. So a PMD entry has a different format than a PTE. Not sure if the proposed scheme would be better for such things were we have to use different accessors depending on the level.

Reworking page-table traversal

willy — Sun, 06 May 2018 17:37:52 +0000

No, it's 5 levels on z/Arch. 11+11+11+11+8+12 =64
x86 uses 9+9+9+9+9+12 = 57 bits

Source: first result on
https://www.google.ca/search?q=zseries+page+table+site%3A...
(Hard to get a direct link to a PDF on Android)

If x86 were willing to switch to an 8k page size, 5 level paging would get them 63 bits.

Reworking page-table traversal

pbonzini — Sat, 05 May 2018 01:20:50 +0000

As far as I know, s390 hardware already supports six level page tables...