| From: |
| Konrad Dybcio <konrad.dybcio-AT-linaro.org> |
| To: |
| Rob Clark <robdclark-AT-gmail.com>, Sean Paul <sean-AT-poorly.run>, Abhinav Kumar <quic_abhinavk-AT-quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov-AT-linaro.org>, David Airlie <airlied-AT-gmail.com>, Daniel Vetter <daniel-AT-ffwll.ch>, Bjorn Andersson <andersson-AT-kernel.org>, Rob Herring <robh-AT-kernel.org>, Krzysztof Kozlowski <krzk+dt-AT-kernel.org>, Conor Dooley <conor+dt-AT-kernel.org> |
| Subject: |
| [PATCH v5 0/5] Add SMEM-based speedbin matching |
| Date: |
| Tue, 09 Jul 2024 12:45:28 +0200 |
| Message-ID: |
| <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> |
| Cc: |
| Marijn Suijten <marijn.suijten-AT-somainline.org>, linux-arm-msm-AT-vger.kernel.org, dri-devel-AT-lists.freedesktop.org, freedreno-AT-lists.freedesktop.org, linux-kernel-AT-vger.kernel.org, devicetree-AT-vger.kernel.org, Konrad Dybcio <konrad.dybcio-AT-linaro.org> |
| Archive-link: |
| Article |
Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore,
but instead rely on a set of combinations of "feature code" (FC) and
"product code" (PC) identifiers to match the bins. This series adds
support for that.
I suppose a qcom/for-soc immutable branch would be in order if we want
to land this in the upcoming cycle.
FWIW I preferred the fuses myself..
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Changes in v5:
- Rebase
- Fix some unhandled cases (Elliot)
- Fix unused variable warning
- Touch up some comments
- Link to v4: https://lore.kernel.org/r/20240625-topic-smem_speedbin-v4...
Changes in v4:
- Drop applied qcom patches
- Make the fuse/speedbin fields u16 again (as Pcode is unused)
- Add comments explaining why there's only speedbin0 for 8550
- Fix some checkpatch fluff (code style)
- Rebase on next-20240625
Changes in v3:
- Wrap the argument usage in new preprocessor macros in braces (Bjorn)
- Make the SOCINFO_FC_INT_MAX define inclusive, adjust .h and .c (Bjorn)
- Pick up rbs
- Rebase on next-20240605
- Drop the already-applied ("Avoid a nullptr dereference when speedbin
setting fails")
Changes in v2:
- Separate moving existing and adding new defines
- Fix kerneldoc copypasta
- Remove some wrong comments and defines
- Remove assumed "max" values for PCs and external FCs
- Improve some commit messages
- Return -EOPNOTSUPP instead of -EINVAL when calling p/fcode getters
on socinfo older than v16
- Drop pcode getters and evaluation (doesn't matter for Adreno on
non-proto SoCs)
- Rework the speedbin logic to be hopefully saner
- Link to v1: https://lore.kernel.org/r/20240405-topic-smem_speedbin-v1...
---
Konrad Dybcio (5):
drm/msm/adreno: Implement SMEM-based speed bin
drm/msm/adreno: Add speedbin data for SM8550 / A740
drm/msm/adreno: Define A530 speed bins explicitly
drm/msm/adreno: Redo the speedbin assignment
arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 +++++++-
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 +++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 ------------
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 54 -------------------
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 85 +++++++++++++++++++++++++++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++-
8 files changed, 119 insertions(+), 97 deletions(-)
---
base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233
change-id: 20240404-topic-smem_speedbin-8deecd0bef0e
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
