| From: |
| Anup Patel <apatel-AT-ventanamicro.com> |
| To: |
| Paolo Bonzini <pbonzini-AT-redhat.com>, Atish Patra <atishp-AT-atishpatra.org>, Palmer Dabbelt <palmer-AT-dabbelt.com>, Paul Walmsley <paul.walmsley-AT-sifive.com>, Conor Dooley <conor-AT-kernel.org>, Rob Herring <robh+dt-AT-kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt-AT-linaro.org>, Shuah Khan <shuah-AT-kernel.org> |
| Subject: |
| [PATCH v3 0/6] KVM RISC-V Conditional Operations |
| Date: |
| Tue, 03 Oct 2023 09:22:20 +0530 |
| Message-ID: |
| <20231003035226.1945725-1-apatel@ventanamicro.com> |
| Cc: |
| Andrew Jones <ajones-AT-ventanamicro.com>, Mayuresh Chitale <mchitale-AT-ventanamicro.com>, devicetree-AT-vger.kernel.org, kvm-AT-vger.kernel.org, kvm-riscv-AT-lists.infradead.org, linux-riscv-AT-lists.infradead.org, linux-kernel-AT-vger.kernel.org, linux-kselftest-AT-vger.kernel.org, Anup Patel <apatel-AT-ventanamicro.com> |
| Archive-link: |
| Article |
This series extends KVM RISC-V to allow Guest/VM discover and use
conditional operations related ISA extensions (namely XVentanaCondOps
and Zicond).
To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
branch at: https://github.com/avpatel/kvmtool.git
These patches are based upon the latest riscv_kvm_queue and can also be
found in the riscv_kvm_condops_v3 branch at:
https://github.com/avpatel/linux.git
Changes since v2:
- Dropped patch1, patch2, and patch5 since these patches don't meet
the requirements of patch acceptance policy.
Changes since v1:
- Rebased the series on riscv_kvm_queue
- Split PATCH1 and PATCH2 of v1 series into two patches
- Added separate test configs for XVentanaCondOps and Zicond in PATCH7
of v1 series.
Anup Patel (6):
dt-bindings: riscv: Add Zicond extension entry
RISC-V: Detect Zicond from ISA string
RISC-V: KVM: Allow Zicond extension for Guest/VM
KVM: riscv: selftests: Add senvcfg register to get-reg-list test
KVM: riscv: selftests: Add smstateen registers to get-reg-list test
KVM: riscv: selftests: Add condops extensions to get-reg-list test
.../devicetree/bindings/riscv/extensions.yaml | 6 +++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 +
.../selftests/kvm/riscv/get-reg-list.c | 54 +++++++++++++++++++
6 files changed, 65 insertions(+)
--
2.34.1
