The search for the correct amount of split-lock misery [LWN.net]

The search for the correct amount of split-lock misery

Posted Oct 21, 2022 10:04 UTC (Fri) by scientes (guest, #83068)
Parent article: The search for the correct amount of split-lock misery

Considering the long history of silicon bugs around "transactional memory" which is basically atomic operations over a much larger amount of multiple cache lines, this is clearly just the "exercise for the reader" warm-up to getting that stuff correct.

Ivan Goddard said that atomic operations rather than the cache-flushing approach is not really worth it, because it costs almost the same due to cache-coherency issues. I have no thought through that however (I can't even get my head around L2 cache-coherent Zync-9000 FPGA with AXI yet...)

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The search for the correct amount of split-lock misery

Posted Oct 23, 2022 17:22 UTC (Sun) by marcH (subscriber, #57642) [Link]

> Considering the long history of silicon bugs around "transactional memory" which is basically atomic operations over a much larger amount of multiple cache lines

Silicon bugs asides, this "basically" sounds weird in a discussion about split lock performance. The concept of a transaction is exactly what provides atomicity over a larger set of data _without_ any extra performance cost. Transactions make performance independent from the data size.