| From: |
| AngeloGioacchino Del Regno <angelogioacchino.delregno-AT-collabora.com> |
| To: |
| robh+dt-AT-kernel.org |
| Subject: |
| [PATCH 0/5] MediaTek Helio X10 MT6795 - Clock drivers |
| Date: |
| Fri, 13 May 2022 18:50:45 +0200 |
| Message-ID: |
| <20220513165050.500831-1-angelogioacchino.delregno@collabora.com> |
| Cc: |
| krzysztof.kozlowski+dt-AT-linaro.org, matthias.bgg-AT-gmail.com, mturquette-AT-baylibre.com, sboyd-AT-kernel.org, p.zabel-AT-pengutronix.de, y.oudjana-AT-protonmail.com, angelogioacchino.delregno-AT-collabora.com, jason-jh.lin-AT-mediatek.com, ck.hu-AT-mediatek.com, fparent-AT-baylibre.com, rex-bc.chen-AT-mediatek.com, tinghan.shen-AT-mediatek.com, chun-jie.chen-AT-mediatek.com, weiyi.lu-AT-mediatek.com, ikjn-AT-chromium.org, miles.chen-AT-mediatek.com, sam.shih-AT-mediatek.com, wenst-AT-chromium.org, bgolaszewski-AT-baylibre.com, devicetree-AT-vger.kernel.org, linux-kernel-AT-vger.kernel.org, linux-arm-kernel-AT-lists.infradead.org, linux-mediatek-AT-lists.infradead.org, linux-clk-AT-vger.kernel.org, konrad.dybcio-AT-somainline.org, marijn.suijten-AT-somainline.org, martin.botka-AT-somainline.org, ~postmarketos/upstreaming-AT-lists.sr.ht, phone-devel-AT-vger.kernel.org, paul.bouchara-AT-somainline.org, kernel-AT-collabora.com |
| Archive-link: |
| Article |
In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.
This (very big) series introduces system clock, multimedia clock drivers
(including resets) for this SoC.
Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone.
AngeloGioacchino Del Regno (5):
dt-bindings: mediatek: Document MT6795 system controllers bindings
dt-bindings: clock: Add MediaTek Helio X10 MT6795 clock bindings
dt-bindings: reset: Add bindings for MT6795 Helio X10 reset
controllers
dt-bindings: arm: mediatek: Add clock driver bindings for MT6795
clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers
.../arm/mediatek/mediatek,infracfg.yaml | 2 +
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
.../arm/mediatek/mediatek,mt6795-clock.yaml | 67 ++
.../mediatek/mediatek,mt6795-sys-clock.yaml | 73 +++
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../bindings/clock/mediatek,apmixedsys.yaml | 1 +
.../bindings/clock/mediatek,topckgen.yaml | 1 +
drivers/clk/mediatek/Kconfig | 37 ++
drivers/clk/mediatek/Makefile | 6 +
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 154 +++++
drivers/clk/mediatek/clk-mt6795-infracfg.c | 145 +++++
drivers/clk/mediatek/clk-mt6795-mfg.c | 47 ++
drivers/clk/mediatek/clk-mt6795-mm.c | 103 +++
drivers/clk/mediatek/clk-mt6795-pericfg.c | 157 +++++
drivers/clk/mediatek/clk-mt6795-topckgen.c | 607 ++++++++++++++++++
drivers/clk/mediatek/clk-mt6795-vdecsys.c | 52 ++
drivers/clk/mediatek/clk-mt6795-vencsys.c | 46 ++
include/dt-bindings/clock/mt6795-clk.h | 275 ++++++++
include/dt-bindings/reset/mt6795-resets.h | 50 ++
19 files changed, 1825 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml
create mode 100644 drivers/clk/mediatek/clk-mt6795-apmixedsys.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-infracfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-mfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-pericfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-topckgen.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-vdecsys.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-vencsys.c
create mode 100644 include/dt-bindings/clock/mt6795-clk.h
create mode 100644 include/dt-bindings/reset/mt6795-resets.h
--
2.35.1
