Thoughts on software-defined silicon

You're assuming that defects in L2/3 can only be worked around by disabling noticable chunks of the CPU. I don't know how Intel handles it, but I'd encourage you to read a paper from HP on how they handled it twenty years ago,

A 500 MHz 1.5 MB cache with on-chip CPU

(there are various free copies of the pdf floating around the net; you don't need to pay for it)

You probably also want to consider what percentage of the die is L3 cache; over 90% on the high end models with a hundred MB of L3 cache.