Thoughts on software-defined silicon [LWN.net]

Thoughts on software-defined silicon

Posted Feb 18, 2022 22:59 UTC (Fri) by jhoblitt (subscriber, #77733)
In reply to: Thoughts on software-defined silicon by kunitz
Parent article: Thoughts on software-defined silicon

Intel will still have to have a huge number of SKUs to make use of the chips with defects in cores, L2, L3, etc.

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Thoughts on software-defined silicon

Posted Feb 19, 2022 13:45 UTC (Sat) by atnot (guest, #124910) [Link] (2 responses)

This is what chip manufacturers always point to, however from people in the industry the reality is that especially as the process matures, most dies are able to hit high bins without issues. There isn't really a technical need for more than two or three SKUs per design. As e.g. AMD has shown by only releasing three real desktop SKUs in the 5000 series.

Thoughts on software-defined silicon

Posted Feb 19, 2022 15:36 UTC (Sat) by jhoblitt (subscriber, #77733) [Link] (1 responses)

I know next to nothing about ICU manufacturing but couldn't that also be a sign as to the differences in TSMC vs Intel defect rates?

Thoughts on software-defined silicon

Posted Feb 19, 2022 23:33 UTC (Sat) by atnot (guest, #124910) [Link]

Unlikely, as there are two major other differences:

1. AMD could not adjust it's wafer allocations to the shortages easily, as TSMC fab capacity has to be booked far in advance. Intel is far more flexible there.

2. More importantly, unlike Intel, AMD shares silicon between server and desktop processors. Since Server CPUs have far higher margins, this means they are going to prioritize those when push comes to shove as it did last year. In such an environment it makes little sense to launch an SKU for every price point as they usually would.

Thoughts on software-defined silicon

Posted Feb 20, 2022 17:13 UTC (Sun) by willy (subscriber, #9762) [Link] (1 responses)

You're assuming that defects in L2/3 can only be worked around by disabling noticable chunks of the CPU. I don't know how Intel handles it, but I'd encourage you to read a paper from HP on how they handled it twenty years ago,

A 500 MHz 1.5 MB cache with on-chip CPU

(there are various free copies of the pdf floating around the net; you don't need to pay for it)

You probably also want to consider what percentage of the die is L3 cache; over 90% on the high end models with a hundred MB of L3 cache.

Thoughts on software-defined silicon

Posted Feb 21, 2022 4:54 UTC (Mon) by willy (subscriber, #9762) [Link]

Sorry, that design didn't feature the redundancy. That was added in the next generation,

https://parisc.wiki.kernel.org/index.php/File:Isscc_cache...

Slide 20 is where they start talking about the yield improvement features.