| From: |
| Atish Patra <atishp-AT-rivosinc.com> |
| To: |
| linux-kernel-AT-vger.kernel.org |
| Subject: |
| [PATCH v2 0/6] Provide a fraemework for RISC-V ISA extensions |
| Date: |
| Thu, 10 Feb 2022 13:40:12 -0800 |
| Message-ID: |
| <20220210214018.55739-1-atishp@rivosinc.com> |
| Cc: |
| Atish Patra <atishp-AT-rivosinc.com>, Albert Ou <aou-AT-eecs.berkeley.edu>, Atish Patra <atishp-AT-atishpatra.org>, Anup Patel <anup-AT-brainfault.org>, Damien Le Moal <damien.lemoal-AT-wdc.com>, devicetree-AT-vger.kernel.org, Jisheng Zhang <jszhang-AT-kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski-AT-canonical.com>, linux-riscv-AT-lists.infradead.org, Palmer Dabbelt <palmer-AT-dabbelt.com>, Paul Walmsley <paul.walmsley-AT-sifive.com>, Rob Herring <robh+dt-AT-kernel.org> |
| Archive-link: |
| Article |
This series implements a generic framework to parse multi-letter ISA
extensions. This series is based on Tsukasa's v3 isa extension improvement
series[1]. I have fixed few bugs and improved comments from that series
(PATCH1-3). I have not used PATCH 4 from that series as we are not using
ISA extension versioning as of now. We can add that later if required.
PATCH 4 allows the probing of multi-letter extensions via a macro.
It continues to use the common isa extensions between all the harts.
Thus hetergenous hart systems will only see the common ISA extensions.
PATCH 6 improves the /proc/cpuinfo interface for the available ISA extensions
via /proc/cpuinfo.
Here is the example output of /proc/cpuinfo:
(with debug patches in Qemu and Linux kernel)
/ # cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdcsu
isa-ext : sstc,sscofpmf
mmu : sv48
processor : 1
hart : 1
isa : rv64imafdcsu
isa-ext : sstc,sscofpmf
mmu : sv48
processor : 2
hart : 2
isa : rv64imafdcsu
isa-ext : sstc,sscofpmf
mmu : sv48
processor : 3
hart : 3
isa : rv64imafdcsu
isa-ext : sstc,sscofpmf
mmu : sv48
Anybody adding support for any new multi-letter extensions should add an
entry to the riscv_isa_ext_id and the isa extension array.
E.g. The patch[2] adds the support for sstc extension.
[1] https://lore.kernel.org/all/0f568515-a05e-8204-aae3-03597...
[2] https://github.com/atishp04/linux/commit/dfc9b0d16f5a6e46...
Changes from v1->v2:
1. Instead of adding a separate DT property use the riscv,isa property.
2. Based on Tsukasa's v3 isa extension improvement series.
Atish Patra (3):
RISC-V: Implement multi-letter ISA extension probing framework
RISC-V: Do no continue isa string parsing without correct XLEN
RISC-V: Improve /proc/cpuinfo output for ISA extensions
Tsukasa OI (3):
RISC-V: Correctly print supported extensions
RISC-V: Minimal parser for "riscv, isa" strings
RISC-V: Extract multi-letter extension names from "riscv,isa"
arch/riscv/include/asm/hwcap.h | 25 +++++++
arch/riscv/kernel/cpu.c | 44 ++++++++++-
arch/riscv/kernel/cpufeature.c | 132 ++++++++++++++++++++++++++++-----
3 files changed, 180 insertions(+), 21 deletions(-)
--
2.30.2