| From: |
| Yifeng Zhao <yifeng.zhao-AT-rock-chips.com> |
| To: |
| heiko-AT-sntech.de |
| Subject: |
| [PATCH v8 0/4] Add Naneng combo PHY support for RK3568 |
| Date: |
| Tue, 08 Feb 2022 17:13:22 +0800 |
| Message-ID: |
| <20220208091326.12495-1-yifeng.zhao@rock-chips.com> |
| Cc: |
| robh+dt-AT-kernel.org, jbx6244-AT-gmail.com, devicetree-AT-vger.kernel.org, vkoul-AT-kernel.org, michael.riesch-AT-wolfvision.net, linux-rockchip-AT-lists.infradead.org, linux-arm-kernel-AT-lists.infradead.org, linux-kernel-AT-vger.kernel.org, linux-phy-AT-lists.infradead.org, kishon-AT-ti.com, p.zabel-AT-pengutronix.de, cl-AT-rock-chips.com, kever.yang-AT-rock-chips.com, lee.jones-AT-linaro.org, wulf-AT-rock-chips.com, david.wu-AT-rock-chips.com, Yifeng Zhao <yifeng.zhao-AT-rock-chips.com> |
| Archive-link: |
| Article |
This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init
Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
- rename regs
Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle
Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name
Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi
Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi
Johan Jonker (1):
dt-bindings: soc: grf: add naneng combo phy register compatible
Yifeng Zhao (3):
dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
phy: rockchip: add naneng combo phy for RK3568
arm64: dts: rockchip: add naneng combo phy nodes for rk3568
.../phy/phy-rockchip-naneng-combphy.yaml | 109 ++++
.../devicetree/bindings/soc/rockchip/grf.yaml | 2 +
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++
drivers/phy/rockchip/Kconfig | 8 +
drivers/phy/rockchip/Makefile | 1 +
.../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++
7 files changed, 769 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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2.17.1
