| From: |
| Vidya Sagar <vidyas-AT-nvidia.com> |
| To: |
| <bhelgaas-AT-google.com>, <lorenzo.pieralisi-AT-arm.com>, <robh+dt-AT-kernel.org>, <thierry.reding-AT-gmail.com>, <jonathanh-AT-nvidia.com> |
| Subject: |
| [PATCH V1 00/10] PCI: tegra: Add Tegra234 PCIe support |
| Date: |
| Sat, 05 Feb 2022 21:51:34 +0530 |
| Message-ID: |
| <20220205162144.30240-1-vidyas@nvidia.com> |
| Cc: |
| <kishon-AT-ti.com>, <vkoul-AT-kernel.org>, <kw-AT-linux.com>, <krzysztof.kozlowski-AT-canonical.com>, <p.zabel-AT-pengutronix.de>, <mperttunen-AT-nvidia.com>, <linux-pci-AT-vger.kernel.org>, <devicetree-AT-vger.kernel.org>, <linux-tegra-AT-vger.kernel.org>, <linux-kernel-AT-vger.kernel.org>, <linux-phy-AT-lists.infradead.org>, <kthota-AT-nvidia.com>, <mmaddireddy-AT-nvidia.com>, <vidyas-AT-nvidia.com>, <sagar.tv-AT-gmail.com> |
| Archive-link: |
| Article |
Tegra234 has a total of 11 PCIe controllers based on Synopsys DesignWare core.
There are three Universal PHY (UPHY) blocks (viz. HSIO, NVHS and GBE) with
each block supporting 8 lanes respectively. Controllers:0~4 use UPHY lanes
from HSIO block, Controllers:5,6 use UPHY lanes from NVHS block and
Controllers:7~10 use UPHY lanes from GBE block. Lane mapping in each block
is controlled in XBAR module by BPMP-FW. Since PCIe core has PIPE interface,
a glue module called PIPE-to-UPHY (P2U) is used to connect each UPHY lane
(applicable to all three UPHY bricks i.e. HSIO/NVHS/GBE) to PCIe controller.
This patch series
- Adds support for Tegra234 in the existing P2U PHY driver
- Adds support for Tegra234 in the existing PCIe platform controller driver
- Adds device tree nodes each PCIe controllers
- Enables nodes applicable to P3737-0000 platform
Testing done on P3737-0000 platform
- PCIe link is up with on-board Broadcom WiFi controller
- PCIe link is up with NVMe drive connected to M.2 Key-M slot and its
functionality is verified
- PCIe link is up with a variety of cards (NICs and USB3.0 add-on cards)
and their functionality is verified
Vidya Sagar (10):
dt-bindings: Add Tegra234 PCIe clocks and resets
dt-bindings: power: Add Tegra234 PCIe power domains
dt-bindings: memory: Add Tegra234 PCIe memory
dt-bindings: PHY: P2U: Add support for Tegra234 P2U block
dt-bindings: PCI: tegra: Add device tree support for Tegra234
arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
arm64: tegra: Enable PCIe slots in P3737-0000 board
phy: tegra: Add PCIe PIPE2UPHY support for Tegra234
PCI: Disable MSI for Tegra234 root ports
PCI: tegra: Add Tegra234 PCIe support
.../bindings/pci/nvidia,tegra194-pcie.txt | 106 ++-
.../bindings/phy/phy-tegra194-p2u.yaml | 17 +-
.../nvidia/tegra234-p3737-0000+p3701-0000.dts | 26 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 743 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-tegra194.c | 409 +++++++---
drivers/pci/quirks.c | 9 +
drivers/phy/tegra/phy-tegra194-p2u.c | 48 +-
include/dt-bindings/clock/tegra234-clock.h | 25 +-
include/dt-bindings/memory/tegra234-mc.h | 64 ++
.../dt-bindings/power/tegra234-powergate.h | 20 +
include/dt-bindings/reset/tegra234-reset.h | 27 +-
11 files changed, 1390 insertions(+), 104 deletions(-)
create mode 100644 include/dt-bindings/power/tegra234-powergate.h
--
2.17.1
